esp32s3/extmem/
core0_acs_cache_int_ena.rs

1#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` reader"]
2pub type R = crate::R<CORE0_ACS_CACHE_INT_ENA_SPEC>;
3#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` writer"]
4pub type W = crate::W<CORE0_ACS_CACHE_INT_ENA_SPEC>;
5#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` reader - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
6pub type CORE0_IBUS_ACS_MSK_IC_R = crate::BitReader;
7#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` writer - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
8pub type CORE0_IBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE0_IBUS_WR_IC` reader - The bit is used to enable interrupt by ibus trying to write icache"]
10pub type CORE0_IBUS_WR_IC_R = crate::BitReader;
11#[doc = "Field `CORE0_IBUS_WR_IC` writer - The bit is used to enable interrupt by ibus trying to write icache"]
12pub type CORE0_IBUS_WR_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE0_IBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
14pub type CORE0_IBUS_REJECT_R = crate::BitReader;
15#[doc = "Field `CORE0_IBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
16pub type CORE0_IBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` reader - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
18pub type CORE0_DBUS_ACS_MSK_DC_R = crate::BitReader;
19#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` writer - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
20pub type CORE0_DBUS_ACS_MSK_DC_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE0_DBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
22pub type CORE0_DBUS_REJECT_R = crate::BitReader;
23#[doc = "Field `CORE0_DBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
24pub type CORE0_DBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
27    #[inline(always)]
28    pub fn core0_ibus_acs_msk_ic(&self) -> CORE0_IBUS_ACS_MSK_IC_R {
29        CORE0_IBUS_ACS_MSK_IC_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
32    #[inline(always)]
33    pub fn core0_ibus_wr_ic(&self) -> CORE0_IBUS_WR_IC_R {
34        CORE0_IBUS_WR_IC_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
37    #[inline(always)]
38    pub fn core0_ibus_reject(&self) -> CORE0_IBUS_REJECT_R {
39        CORE0_IBUS_REJECT_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
42    #[inline(always)]
43    pub fn core0_dbus_acs_msk_dc(&self) -> CORE0_DBUS_ACS_MSK_DC_R {
44        CORE0_DBUS_ACS_MSK_DC_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
47    #[inline(always)]
48    pub fn core0_dbus_reject(&self) -> CORE0_DBUS_REJECT_R {
49        CORE0_DBUS_REJECT_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
56            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
57            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
58            .field("core0_ibus_reject", &self.core0_ibus_reject())
59            .field("core0_dbus_acs_msk_dc", &self.core0_dbus_acs_msk_dc())
60            .field("core0_dbus_reject", &self.core0_dbus_reject())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
66    #[inline(always)]
67    pub fn core0_ibus_acs_msk_ic(
68        &mut self,
69    ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
70        CORE0_IBUS_ACS_MSK_IC_W::new(self, 0)
71    }
72    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
73    #[inline(always)]
74    pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
75        CORE0_IBUS_WR_IC_W::new(self, 1)
76    }
77    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
78    #[inline(always)]
79    pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
80        CORE0_IBUS_REJECT_W::new(self, 2)
81    }
82    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access."]
83    #[inline(always)]
84    pub fn core0_dbus_acs_msk_dc(
85        &mut self,
86    ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
87        CORE0_DBUS_ACS_MSK_DC_W::new(self, 3)
88    }
89    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
90    #[inline(always)]
91    pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
92        CORE0_DBUS_REJECT_W::new(self, 4)
93    }
94}
95#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct CORE0_ACS_CACHE_INT_ENA_SPEC;
97impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ENA_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`core0_acs_cache_int_ena::R`](R) reader structure"]
101impl crate::Readable for CORE0_ACS_CACHE_INT_ENA_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`core0_acs_cache_int_ena::W`](W) writer structure"]
103impl crate::Writable for CORE0_ACS_CACHE_INT_ENA_SPEC {
104    type Safety = crate::Unsafe;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107}
108#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_ENA to value 0"]
109impl crate::Resettable for CORE0_ACS_CACHE_INT_ENA_SPEC {
110    const RESET_VALUE: u32 = 0;
111}
esp32s3/extmem/core0_acs_cache_int_ena.rs

esp32s3/extmem/
core0_acs_cache_int_ena.rs
