esp32s3/usb0/
pcgcctl.rs

1#[doc = "Register `PCGCCTL` reader"]
2pub type R = crate::R<PCGCCTL_SPEC>;
3#[doc = "Register `PCGCCTL` writer"]
4pub type W = crate::W<PCGCCTL_SPEC>;
5#[doc = "Field `STOPPCLK` reader - "]
6pub type STOPPCLK_R = crate::BitReader;
7#[doc = "Field `STOPPCLK` writer - "]
8pub type STOPPCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `GATEHCLK` reader - "]
10pub type GATEHCLK_R = crate::BitReader;
11#[doc = "Field `GATEHCLK` writer - "]
12pub type GATEHCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PWRCLMP` reader - "]
14pub type PWRCLMP_R = crate::BitReader;
15#[doc = "Field `PWRCLMP` writer - "]
16pub type PWRCLMP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RSTPDWNMODULE` reader - "]
18pub type RSTPDWNMODULE_R = crate::BitReader;
19#[doc = "Field `RSTPDWNMODULE` writer - "]
20pub type RSTPDWNMODULE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `PHYSLEEP` reader - "]
22pub type PHYSLEEP_R = crate::BitReader;
23#[doc = "Field `L1SUSPENDED` reader - "]
24pub type L1SUSPENDED_R = crate::BitReader;
25#[doc = "Field `RESETAFTERSUSP` reader - "]
26pub type RESETAFTERSUSP_R = crate::BitReader;
27#[doc = "Field `RESETAFTERSUSP` writer - "]
28pub type RESETAFTERSUSP_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0"]
31    #[inline(always)]
32    pub fn stoppclk(&self) -> STOPPCLK_R {
33        STOPPCLK_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1"]
36    #[inline(always)]
37    pub fn gatehclk(&self) -> GATEHCLK_R {
38        GATEHCLK_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2"]
41    #[inline(always)]
42    pub fn pwrclmp(&self) -> PWRCLMP_R {
43        PWRCLMP_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3"]
46    #[inline(always)]
47    pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R {
48        RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 6"]
51    #[inline(always)]
52    pub fn physleep(&self) -> PHYSLEEP_R {
53        PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0)
54    }
55    #[doc = "Bit 7"]
56    #[inline(always)]
57    pub fn l1suspended(&self) -> L1SUSPENDED_R {
58        L1SUSPENDED_R::new(((self.bits >> 7) & 1) != 0)
59    }
60    #[doc = "Bit 8"]
61    #[inline(always)]
62    pub fn resetaftersusp(&self) -> RESETAFTERSUSP_R {
63        RESETAFTERSUSP_R::new(((self.bits >> 8) & 1) != 0)
64    }
65}
66#[cfg(feature = "impl-register-debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("PCGCCTL")
70            .field("stoppclk", &self.stoppclk())
71            .field("gatehclk", &self.gatehclk())
72            .field("pwrclmp", &self.pwrclmp())
73            .field("rstpdwnmodule", &self.rstpdwnmodule())
74            .field("physleep", &self.physleep())
75            .field("l1suspended", &self.l1suspended())
76            .field("resetaftersusp", &self.resetaftersusp())
77            .finish()
78    }
79}
80impl W {
81    #[doc = "Bit 0"]
82    #[inline(always)]
83    pub fn stoppclk(&mut self) -> STOPPCLK_W<PCGCCTL_SPEC> {
84        STOPPCLK_W::new(self, 0)
85    }
86    #[doc = "Bit 1"]
87    #[inline(always)]
88    pub fn gatehclk(&mut self) -> GATEHCLK_W<PCGCCTL_SPEC> {
89        GATEHCLK_W::new(self, 1)
90    }
91    #[doc = "Bit 2"]
92    #[inline(always)]
93    pub fn pwrclmp(&mut self) -> PWRCLMP_W<PCGCCTL_SPEC> {
94        PWRCLMP_W::new(self, 2)
95    }
96    #[doc = "Bit 3"]
97    #[inline(always)]
98    pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<PCGCCTL_SPEC> {
99        RSTPDWNMODULE_W::new(self, 3)
100    }
101    #[doc = "Bit 8"]
102    #[inline(always)]
103    pub fn resetaftersusp(&mut self) -> RESETAFTERSUSP_W<PCGCCTL_SPEC> {
104        RESETAFTERSUSP_W::new(self, 8)
105    }
106}
107#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`pcgcctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pcgcctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
108pub struct PCGCCTL_SPEC;
109impl crate::RegisterSpec for PCGCCTL_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [`pcgcctl::R`](R) reader structure"]
113impl crate::Readable for PCGCCTL_SPEC {}
114#[doc = "`write(|w| ..)` method takes [`pcgcctl::W`](W) writer structure"]
115impl crate::Writable for PCGCCTL_SPEC {
116    type Safety = crate::Unsafe;
117    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
119}
120#[doc = "`reset()` method sets PCGCCTL to value 0"]
121impl crate::Resettable for PCGCCTL_SPEC {
122    const RESET_VALUE: u32 = 0;
123}
esp32s3/usb0/pcgcctl.rs

esp32s3/usb0/
pcgcctl.rs
