esp32s3/uhci0/
app_int_set.rs

1#[doc = "Register `APP_INT_SET` writer"]
2pub type W = crate::W<APP_INT_SET_SPEC>;
3#[doc = "Field `APP_CTRL0_INT_SET` writer - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT."]
4pub type APP_CTRL0_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `APP_CTRL1_INT_SET` writer - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT."]
6pub type APP_CTRL1_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[cfg(feature = "impl-register-debug")]
8impl core::fmt::Debug for crate::generic::Reg<APP_INT_SET_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        write!(f, "(not readable)")
11    }
12}
13impl W {
14    #[doc = "Bit 0 - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT."]
15    #[inline(always)]
16    pub fn app_ctrl0_int_set(&mut self) -> APP_CTRL0_INT_SET_W<APP_INT_SET_SPEC> {
17        APP_CTRL0_INT_SET_W::new(self, 0)
18    }
19    #[doc = "Bit 1 - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT."]
20    #[inline(always)]
21    pub fn app_ctrl1_int_set(&mut self) -> APP_CTRL1_INT_SET_W<APP_INT_SET_SPEC> {
22        APP_CTRL1_INT_SET_W::new(self, 1)
23    }
24}
25#[doc = "Software interrupt trigger source\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_int_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26pub struct APP_INT_SET_SPEC;
27impl crate::RegisterSpec for APP_INT_SET_SPEC {
28    type Ux = u32;
29}
30#[doc = "`write(|w| ..)` method takes [`app_int_set::W`](W) writer structure"]
31impl crate::Writable for APP_INT_SET_SPEC {
32    type Safety = crate::Unsafe;
33    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35}
36#[doc = "`reset()` method sets APP_INT_SET to value 0"]
37impl crate::Resettable for APP_INT_SET_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
esp32s3/uhci0/app_int_set.rs

esp32s3/uhci0/
app_int_set.rs
