esp32s3/spi0/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `TOTAL_TRANS_END` reader - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
6pub type TOTAL_TRANS_END_R = crate::BitReader;
7#[doc = "Field `TOTAL_TRANS_END` writer - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
8pub type TOTAL_TRANS_END_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ECC_ERR` reader - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."]
10pub type ECC_ERR_R = crate::BitReader;
11#[doc = "Field `ECC_ERR` writer - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."]
12pub type ECC_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 2 - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
15    #[inline(always)]
16    pub fn total_trans_end(&self) -> TOTAL_TRANS_END_R {
17        TOTAL_TRANS_END_R::new(((self.bits >> 2) & 1) != 0)
18    }
19    #[doc = "Bit 4 - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."]
20    #[inline(always)]
21    pub fn ecc_err(&self) -> ECC_ERR_R {
22        ECC_ERR_R::new(((self.bits >> 4) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("INT_ENA")
29            .field("total_trans_end", &self.total_trans_end())
30            .field("ecc_err", &self.ecc_err())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bit 2 - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
36    #[inline(always)]
37    pub fn total_trans_end(&mut self) -> TOTAL_TRANS_END_W<INT_ENA_SPEC> {
38        TOTAL_TRANS_END_W::new(self, 2)
39    }
40    #[doc = "Bit 4 - The enable bit for SPI_MEM_ECC_ERR_INT interrupt."]
41    #[inline(always)]
42    pub fn ecc_err(&mut self) -> ECC_ERR_W<INT_ENA_SPEC> {
43        ECC_ERR_W::new(self, 4)
44    }
45}
46#[doc = "SPI1 interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct INT_ENA_SPEC;
48impl crate::RegisterSpec for INT_ENA_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
52impl crate::Readable for INT_ENA_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
54impl crate::Writable for INT_ENA_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets INT_ENA to value 0"]
60impl crate::Resettable for INT_ENA_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32s3/spi0/int_ena.rs

esp32s3/spi0/
int_ena.rs
