esp32s3/spi0/
dout_mode.rs

1#[doc = "Register `DOUT_MODE` reader"]
2pub type R = crate::R<DOUT_MODE_SPEC>;
3#[doc = "Register `DOUT_MODE` writer"]
4pub type W = crate::W<DOUT_MODE_SPEC>;
5#[doc = "Field `DOUT0_MODE` reader - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
6pub type DOUT0_MODE_R = crate::BitReader;
7#[doc = "Field `DOUT0_MODE` writer - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
8pub type DOUT0_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DOUT1_MODE` reader - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
10pub type DOUT1_MODE_R = crate::BitReader;
11#[doc = "Field `DOUT1_MODE` writer - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
12pub type DOUT1_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DOUT2_MODE` reader - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
14pub type DOUT2_MODE_R = crate::BitReader;
15#[doc = "Field `DOUT2_MODE` writer - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
16pub type DOUT2_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DOUT3_MODE` reader - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
18pub type DOUT3_MODE_R = crate::BitReader;
19#[doc = "Field `DOUT3_MODE` writer - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
20pub type DOUT3_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DOUT4_MODE` reader - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
22pub type DOUT4_MODE_R = crate::BitReader;
23#[doc = "Field `DOUT4_MODE` writer - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
24pub type DOUT4_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DOUT5_MODE` reader - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
26pub type DOUT5_MODE_R = crate::BitReader;
27#[doc = "Field `DOUT5_MODE` writer - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
28pub type DOUT5_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DOUT6_MODE` reader - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
30pub type DOUT6_MODE_R = crate::BitReader;
31#[doc = "Field `DOUT6_MODE` writer - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
32pub type DOUT6_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DOUT7_MODE` reader - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
34pub type DOUT7_MODE_R = crate::BitReader;
35#[doc = "Field `DOUT7_MODE` writer - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
36pub type DOUT7_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DOUTS_MODE` reader - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
38pub type DOUTS_MODE_R = crate::BitReader;
39#[doc = "Field `DOUTS_MODE` writer - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
40pub type DOUTS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
43    #[inline(always)]
44    pub fn dout0_mode(&self) -> DOUT0_MODE_R {
45        DOUT0_MODE_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
48    #[inline(always)]
49    pub fn dout1_mode(&self) -> DOUT1_MODE_R {
50        DOUT1_MODE_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
53    #[inline(always)]
54    pub fn dout2_mode(&self) -> DOUT2_MODE_R {
55        DOUT2_MODE_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
58    #[inline(always)]
59    pub fn dout3_mode(&self) -> DOUT3_MODE_R {
60        DOUT3_MODE_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
63    #[inline(always)]
64    pub fn dout4_mode(&self) -> DOUT4_MODE_R {
65        DOUT4_MODE_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
68    #[inline(always)]
69    pub fn dout5_mode(&self) -> DOUT5_MODE_R {
70        DOUT5_MODE_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
73    #[inline(always)]
74    pub fn dout6_mode(&self) -> DOUT6_MODE_R {
75        DOUT6_MODE_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
78    #[inline(always)]
79    pub fn dout7_mode(&self) -> DOUT7_MODE_R {
80        DOUT7_MODE_R::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 8 - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
83    #[inline(always)]
84    pub fn douts_mode(&self) -> DOUTS_MODE_R {
85        DOUTS_MODE_R::new(((self.bits >> 8) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("DOUT_MODE")
92            .field("dout0_mode", &self.dout0_mode())
93            .field("dout1_mode", &self.dout1_mode())
94            .field("dout2_mode", &self.dout2_mode())
95            .field("dout3_mode", &self.dout3_mode())
96            .field("dout4_mode", &self.dout4_mode())
97            .field("dout5_mode", &self.dout5_mode())
98            .field("dout6_mode", &self.dout6_mode())
99            .field("dout7_mode", &self.dout7_mode())
100            .field("douts_mode", &self.douts_mode())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
106    #[inline(always)]
107    pub fn dout0_mode(&mut self) -> DOUT0_MODE_W<DOUT_MODE_SPEC> {
108        DOUT0_MODE_W::new(self, 0)
109    }
110    #[doc = "Bit 1 - SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
111    #[inline(always)]
112    pub fn dout1_mode(&mut self) -> DOUT1_MODE_W<DOUT_MODE_SPEC> {
113        DOUT1_MODE_W::new(self, 1)
114    }
115    #[doc = "Bit 2 - SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
116    #[inline(always)]
117    pub fn dout2_mode(&mut self) -> DOUT2_MODE_W<DOUT_MODE_SPEC> {
118        DOUT2_MODE_W::new(self, 2)
119    }
120    #[doc = "Bit 3 - SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
121    #[inline(always)]
122    pub fn dout3_mode(&mut self) -> DOUT3_MODE_W<DOUT_MODE_SPEC> {
123        DOUT3_MODE_W::new(self, 3)
124    }
125    #[doc = "Bit 4 - SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
126    #[inline(always)]
127    pub fn dout4_mode(&mut self) -> DOUT4_MODE_W<DOUT_MODE_SPEC> {
128        DOUT4_MODE_W::new(self, 4)
129    }
130    #[doc = "Bit 5 - SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
131    #[inline(always)]
132    pub fn dout5_mode(&mut self) -> DOUT5_MODE_W<DOUT_MODE_SPEC> {
133        DOUT5_MODE_W::new(self, 5)
134    }
135    #[doc = "Bit 6 - SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
136    #[inline(always)]
137    pub fn dout6_mode(&mut self) -> DOUT6_MODE_W<DOUT_MODE_SPEC> {
138        DOUT6_MODE_W::new(self, 6)
139    }
140    #[doc = "Bit 7 - SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
141    #[inline(always)]
142    pub fn dout7_mode(&mut self) -> DOUT7_MODE_W<DOUT_MODE_SPEC> {
143        DOUT7_MODE_W::new(self, 7)
144    }
145    #[doc = "Bit 8 - SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
146    #[inline(always)]
147    pub fn douts_mode(&mut self) -> DOUTS_MODE_W<DOUT_MODE_SPEC> {
148        DOUTS_MODE_W::new(self, 8)
149    }
150}
151#[doc = "MSPI output timing delay mode control register when accesses to flash.\n\nYou can [`read`](crate::Reg::read) this register and get [`dout_mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dout_mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct DOUT_MODE_SPEC;
153impl crate::RegisterSpec for DOUT_MODE_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`dout_mode::R`](R) reader structure"]
157impl crate::Readable for DOUT_MODE_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`dout_mode::W`](W) writer structure"]
159impl crate::Writable for DOUT_MODE_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets DOUT_MODE to value 0"]
165impl crate::Resettable for DOUT_MODE_SPEC {
166    const RESET_VALUE: u32 = 0;
167}
esp32s3/spi0/dout_mode.rs

esp32s3/spi0/
dout_mode.rs
