esp32s3/rmt/
ch_rx_conf1.rs

1#[doc = "Register `CH%s_RX_CONF1` reader"]
2pub type R = crate::R<CH_RX_CONF1_SPEC>;
3#[doc = "Register `CH%s_RX_CONF1` writer"]
4pub type W = crate::W<CH_RX_CONF1_SPEC>;
5#[doc = "Field `RX_EN` reader - Set this bit to enable receiver to receive data on CHANNEL%s."]
6pub type RX_EN_R = crate::BitReader;
7#[doc = "Field `RX_EN` writer - Set this bit to enable receiver to receive data on CHANNEL%s."]
8pub type RX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MEM_WR_RST` writer - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."]
10pub type MEM_WR_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `APB_MEM_RST` writer - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."]
12pub type APB_MEM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MEM_OWNER` reader - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."]
14pub type MEM_OWNER_R = crate::BitReader;
15#[doc = "Field `MEM_OWNER` writer - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."]
16pub type MEM_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FILTER_EN` reader - This is the receive filter's enable bit for CHANNEL%s."]
18pub type RX_FILTER_EN_R = crate::BitReader;
19#[doc = "Field `RX_FILTER_EN` writer - This is the receive filter's enable bit for CHANNEL%s."]
20pub type RX_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RX_FILTER_THRES` reader - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
22pub type RX_FILTER_THRES_R = crate::FieldReader;
23#[doc = "Field `RX_FILTER_THRES` writer - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
24pub type RX_FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `MEM_RX_WRAP_EN` reader - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."]
26pub type MEM_RX_WRAP_EN_R = crate::BitReader;
27#[doc = "Field `MEM_RX_WRAP_EN` writer - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."]
28pub type MEM_RX_WRAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `AFIFO_RST` writer - Reserved"]
30pub type AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CONF_UPDATE` writer - synchronization bit for CHANNEL%s"]
32pub type CONF_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
35    #[inline(always)]
36    pub fn rx_en(&self) -> RX_EN_R {
37        RX_EN_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 3 - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."]
40    #[inline(always)]
41    pub fn mem_owner(&self) -> MEM_OWNER_R {
42        MEM_OWNER_R::new(((self.bits >> 3) & 1) != 0)
43    }
44    #[doc = "Bit 4 - This is the receive filter's enable bit for CHANNEL%s."]
45    #[inline(always)]
46    pub fn rx_filter_en(&self) -> RX_FILTER_EN_R {
47        RX_FILTER_EN_R::new(((self.bits >> 4) & 1) != 0)
48    }
49    #[doc = "Bits 5:12 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
50    #[inline(always)]
51    pub fn rx_filter_thres(&self) -> RX_FILTER_THRES_R {
52        RX_FILTER_THRES_R::new(((self.bits >> 5) & 0xff) as u8)
53    }
54    #[doc = "Bit 13 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."]
55    #[inline(always)]
56    pub fn mem_rx_wrap_en(&self) -> MEM_RX_WRAP_EN_R {
57        MEM_RX_WRAP_EN_R::new(((self.bits >> 13) & 1) != 0)
58    }
59}
60#[cfg(feature = "impl-register-debug")]
61impl core::fmt::Debug for R {
62    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
63        f.debug_struct("CH_RX_CONF1")
64            .field("rx_en", &self.rx_en())
65            .field("mem_owner", &self.mem_owner())
66            .field("rx_filter_en", &self.rx_filter_en())
67            .field("rx_filter_thres", &self.rx_filter_thres())
68            .field("mem_rx_wrap_en", &self.mem_rx_wrap_en())
69            .finish()
70    }
71}
72impl W {
73    #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
74    #[inline(always)]
75    pub fn rx_en(&mut self) -> RX_EN_W<CH_RX_CONF1_SPEC> {
76        RX_EN_W::new(self, 0)
77    }
78    #[doc = "Bit 1 - Set this bit to reset write ram address for CHANNEL%s by accessing receiver."]
79    #[inline(always)]
80    pub fn mem_wr_rst(&mut self) -> MEM_WR_RST_W<CH_RX_CONF1_SPEC> {
81        MEM_WR_RST_W::new(self, 1)
82    }
83    #[doc = "Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo."]
84    #[inline(always)]
85    pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<CH_RX_CONF1_SPEC> {
86        APB_MEM_RST_W::new(self, 2)
87    }
88    #[doc = "Bit 3 - This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram."]
89    #[inline(always)]
90    pub fn mem_owner(&mut self) -> MEM_OWNER_W<CH_RX_CONF1_SPEC> {
91        MEM_OWNER_W::new(self, 3)
92    }
93    #[doc = "Bit 4 - This is the receive filter's enable bit for CHANNEL%s."]
94    #[inline(always)]
95    pub fn rx_filter_en(&mut self) -> RX_FILTER_EN_W<CH_RX_CONF1_SPEC> {
96        RX_FILTER_EN_W::new(self, 4)
97    }
98    #[doc = "Bits 5:12 - Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode)."]
99    #[inline(always)]
100    pub fn rx_filter_thres(&mut self) -> RX_FILTER_THRES_W<CH_RX_CONF1_SPEC> {
101        RX_FILTER_THRES_W::new(self, 5)
102    }
103    #[doc = "Bit 13 - This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size."]
104    #[inline(always)]
105    pub fn mem_rx_wrap_en(&mut self) -> MEM_RX_WRAP_EN_W<CH_RX_CONF1_SPEC> {
106        MEM_RX_WRAP_EN_W::new(self, 13)
107    }
108    #[doc = "Bit 14 - Reserved"]
109    #[inline(always)]
110    pub fn afifo_rst(&mut self) -> AFIFO_RST_W<CH_RX_CONF1_SPEC> {
111        AFIFO_RST_W::new(self, 14)
112    }
113    #[doc = "Bit 15 - synchronization bit for CHANNEL%s"]
114    #[inline(always)]
115    pub fn conf_update(&mut self) -> CONF_UPDATE_W<CH_RX_CONF1_SPEC> {
116        CONF_UPDATE_W::new(self, 15)
117    }
118}
119#[doc = "Channel %s configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_rx_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_rx_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
120pub struct CH_RX_CONF1_SPEC;
121impl crate::RegisterSpec for CH_RX_CONF1_SPEC {
122    type Ux = u32;
123}
124#[doc = "`read()` method returns [`ch_rx_conf1::R`](R) reader structure"]
125impl crate::Readable for CH_RX_CONF1_SPEC {}
126#[doc = "`write(|w| ..)` method takes [`ch_rx_conf1::W`](W) writer structure"]
127impl crate::Writable for CH_RX_CONF1_SPEC {
128    type Safety = crate::Unsafe;
129    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
130    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
131}
132#[doc = "`reset()` method sets CH%s_RX_CONF1 to value 0x01e8"]
133impl crate::Resettable for CH_RX_CONF1_SPEC {
134    const RESET_VALUE: u32 = 0x01e8;
135}
esp32s3/rmt/ch_rx_conf1.rs

esp32s3/rmt/
ch_rx_conf1.rs
