esp32s3/i2s0/
tx_timing.rs

1#[doc = "Register `TX_TIMING` reader"]
2pub type R = crate::R<TX_TIMING_SPEC>;
3#[doc = "Register `TX_TIMING` writer"]
4pub type W = crate::W<TX_TIMING_SPEC>;
5#[doc = "Field `TX_SD_OUT_DM` reader - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
6pub type TX_SD_OUT_DM_R = crate::FieldReader;
7#[doc = "Field `TX_SD_OUT_DM` writer - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
8pub type TX_SD_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `TX_SD1_OUT_DM` reader - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
10pub type TX_SD1_OUT_DM_R = crate::FieldReader;
11#[doc = "Field `TX_SD1_OUT_DM` writer - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
12pub type TX_SD1_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `TX_WS_OUT_DM` reader - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
14pub type TX_WS_OUT_DM_R = crate::FieldReader;
15#[doc = "Field `TX_WS_OUT_DM` writer - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
16pub type TX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `TX_BCK_OUT_DM` reader - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
18pub type TX_BCK_OUT_DM_R = crate::FieldReader;
19#[doc = "Field `TX_BCK_OUT_DM` writer - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
20pub type TX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `TX_WS_IN_DM` reader - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
22pub type TX_WS_IN_DM_R = crate::FieldReader;
23#[doc = "Field `TX_WS_IN_DM` writer - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
24pub type TX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `TX_BCK_IN_DM` reader - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
26pub type TX_BCK_IN_DM_R = crate::FieldReader;
27#[doc = "Field `TX_BCK_IN_DM` writer - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
28pub type TX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29impl R {
30    #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
31    #[inline(always)]
32    pub fn tx_sd_out_dm(&self) -> TX_SD_OUT_DM_R {
33        TX_SD_OUT_DM_R::new((self.bits & 3) as u8)
34    }
35    #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
36    #[inline(always)]
37    pub fn tx_sd1_out_dm(&self) -> TX_SD1_OUT_DM_R {
38        TX_SD1_OUT_DM_R::new(((self.bits >> 4) & 3) as u8)
39    }
40    #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
41    #[inline(always)]
42    pub fn tx_ws_out_dm(&self) -> TX_WS_OUT_DM_R {
43        TX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8)
44    }
45    #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
46    #[inline(always)]
47    pub fn tx_bck_out_dm(&self) -> TX_BCK_OUT_DM_R {
48        TX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8)
49    }
50    #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
51    #[inline(always)]
52    pub fn tx_ws_in_dm(&self) -> TX_WS_IN_DM_R {
53        TX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8)
54    }
55    #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
56    #[inline(always)]
57    pub fn tx_bck_in_dm(&self) -> TX_BCK_IN_DM_R {
58        TX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("TX_TIMING")
65            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
66            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
67            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
68            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
69            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
70            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
76    #[inline(always)]
77    pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<TX_TIMING_SPEC> {
78        TX_SD_OUT_DM_W::new(self, 0)
79    }
80    #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
81    #[inline(always)]
82    pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<TX_TIMING_SPEC> {
83        TX_SD1_OUT_DM_W::new(self, 4)
84    }
85    #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
86    #[inline(always)]
87    pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<TX_TIMING_SPEC> {
88        TX_WS_OUT_DM_W::new(self, 16)
89    }
90    #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
91    #[inline(always)]
92    pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<TX_TIMING_SPEC> {
93        TX_BCK_OUT_DM_W::new(self, 20)
94    }
95    #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
96    #[inline(always)]
97    pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<TX_TIMING_SPEC> {
98        TX_WS_IN_DM_W::new(self, 24)
99    }
100    #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
101    #[inline(always)]
102    pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<TX_TIMING_SPEC> {
103        TX_BCK_IN_DM_W::new(self, 28)
104    }
105}
106#[doc = "I2S TX timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct TX_TIMING_SPEC;
108impl crate::RegisterSpec for TX_TIMING_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`tx_timing::R`](R) reader structure"]
112impl crate::Readable for TX_TIMING_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`tx_timing::W`](W) writer structure"]
114impl crate::Writable for TX_TIMING_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets TX_TIMING to value 0"]
120impl crate::Resettable for TX_TIMING_SPEC {
121    const RESET_VALUE: u32 = 0;
122}
esp32s3/i2s0/tx_timing.rs

esp32s3/i2s0/
tx_timing.rs
