esp32s3/extmem/
icache_freeze.rs

1#[doc = "Register `ICACHE_FREEZE` reader"]
2pub type R = crate::R<ICACHE_FREEZE_SPEC>;
3#[doc = "Register `ICACHE_FREEZE` writer"]
4pub type W = crate::W<ICACHE_FREEZE_SPEC>;
5#[doc = "Field `ENA` reader - The bit is used to enable icache freeze mode"]
6pub type ENA_R = crate::BitReader;
7#[doc = "Field `ENA` writer - The bit is used to enable icache freeze mode"]
8pub type ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MODE` reader - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
10pub type MODE_R = crate::BitReader;
11#[doc = "Field `MODE` writer - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
12pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DONE` reader - The bit is used to indicate icache freeze success"]
14pub type DONE_R = crate::BitReader;
15impl R {
16    #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
17    #[inline(always)]
18    pub fn ena(&self) -> ENA_R {
19        ENA_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
22    #[inline(always)]
23    pub fn mode(&self) -> MODE_R {
24        MODE_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - The bit is used to indicate icache freeze success"]
27    #[inline(always)]
28    pub fn done(&self) -> DONE_R {
29        DONE_R::new(((self.bits >> 2) & 1) != 0)
30    }
31}
32#[cfg(feature = "impl-register-debug")]
33impl core::fmt::Debug for R {
34    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
35        f.debug_struct("ICACHE_FREEZE")
36            .field("ena", &self.ena())
37            .field("mode", &self.mode())
38            .field("done", &self.done())
39            .finish()
40    }
41}
42impl W {
43    #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
44    #[inline(always)]
45    pub fn ena(&mut self) -> ENA_W<ICACHE_FREEZE_SPEC> {
46        ENA_W::new(self, 0)
47    }
48    #[doc = "Bit 1 - The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss"]
49    #[inline(always)]
50    pub fn mode(&mut self) -> MODE_W<ICACHE_FREEZE_SPEC> {
51        MODE_W::new(self, 1)
52    }
53}
54#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_freeze::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_freeze::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
55pub struct ICACHE_FREEZE_SPEC;
56impl crate::RegisterSpec for ICACHE_FREEZE_SPEC {
57    type Ux = u32;
58}
59#[doc = "`read()` method returns [`icache_freeze::R`](R) reader structure"]
60impl crate::Readable for ICACHE_FREEZE_SPEC {}
61#[doc = "`write(|w| ..)` method takes [`icache_freeze::W`](W) writer structure"]
62impl crate::Writable for ICACHE_FREEZE_SPEC {
63    type Safety = crate::Unsafe;
64    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
66}
67#[doc = "`reset()` method sets ICACHE_FREEZE to value 0x04"]
68impl crate::Resettable for ICACHE_FREEZE_SPEC {
69    const RESET_VALUE: u32 = 0x04;
70}
esp32s3/extmem/icache_freeze.rs

esp32s3/extmem/
icache_freeze.rs
