esp32s3/extmem/
cache_ilg_int_ena.rs

1#[doc = "Register `CACHE_ILG_INT_ENA` reader"]
2pub type R = crate::R<CACHE_ILG_INT_ENA_SPEC>;
3#[doc = "Register `CACHE_ILG_INT_ENA` writer"]
4pub type W = crate::W<CACHE_ILG_INT_ENA_SPEC>;
5#[doc = "Field `ICACHE_SYNC_OP_FAULT` reader - The bit is used to enable interrupt by sync configurations fault."]
6pub type ICACHE_SYNC_OP_FAULT_R = crate::BitReader;
7#[doc = "Field `ICACHE_SYNC_OP_FAULT` writer - The bit is used to enable interrupt by sync configurations fault."]
8pub type ICACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` reader - The bit is used to enable interrupt by preload configurations fault."]
10pub type ICACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
11#[doc = "Field `ICACHE_PRELOAD_OP_FAULT` writer - The bit is used to enable interrupt by preload configurations fault."]
12pub type ICACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `DCACHE_SYNC_OP_FAULT` reader - The bit is used to enable interrupt by sync configurations fault."]
14pub type DCACHE_SYNC_OP_FAULT_R = crate::BitReader;
15#[doc = "Field `DCACHE_SYNC_OP_FAULT` writer - The bit is used to enable interrupt by sync configurations fault."]
16pub type DCACHE_SYNC_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` reader - The bit is used to enable interrupt by preload configurations fault."]
18pub type DCACHE_PRELOAD_OP_FAULT_R = crate::BitReader;
19#[doc = "Field `DCACHE_PRELOAD_OP_FAULT` writer - The bit is used to enable interrupt by preload configurations fault."]
20pub type DCACHE_PRELOAD_OP_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DCACHE_WRITE_FLASH` reader - The bit is used to enable interrupt by dcache trying to write flash."]
22pub type DCACHE_WRITE_FLASH_R = crate::BitReader;
23#[doc = "Field `DCACHE_WRITE_FLASH` writer - The bit is used to enable interrupt by dcache trying to write flash."]
24pub type DCACHE_WRITE_FLASH_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MMU_ENTRY_FAULT` reader - The bit is used to enable interrupt by mmu entry fault."]
26pub type MMU_ENTRY_FAULT_R = crate::BitReader;
27#[doc = "Field `MMU_ENTRY_FAULT` writer - The bit is used to enable interrupt by mmu entry fault."]
28pub type MMU_ENTRY_FAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `DCACHE_OCCUPY_EXC` reader - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
30pub type DCACHE_OCCUPY_EXC_R = crate::BitReader;
31#[doc = "Field `DCACHE_OCCUPY_EXC` writer - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
32pub type DCACHE_OCCUPY_EXC_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IBUS_CNT_OVF` reader - The bit is used to enable interrupt by ibus counter overflow."]
34pub type IBUS_CNT_OVF_R = crate::BitReader;
35#[doc = "Field `IBUS_CNT_OVF` writer - The bit is used to enable interrupt by ibus counter overflow."]
36pub type IBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DBUS_CNT_OVF` reader - The bit is used to enable interrupt by dbus counter overflow."]
38pub type DBUS_CNT_OVF_R = crate::BitReader;
39#[doc = "Field `DBUS_CNT_OVF` writer - The bit is used to enable interrupt by dbus counter overflow."]
40pub type DBUS_CNT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
43    #[inline(always)]
44    pub fn icache_sync_op_fault(&self) -> ICACHE_SYNC_OP_FAULT_R {
45        ICACHE_SYNC_OP_FAULT_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
48    #[inline(always)]
49    pub fn icache_preload_op_fault(&self) -> ICACHE_PRELOAD_OP_FAULT_R {
50        ICACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - The bit is used to enable interrupt by sync configurations fault."]
53    #[inline(always)]
54    pub fn dcache_sync_op_fault(&self) -> DCACHE_SYNC_OP_FAULT_R {
55        DCACHE_SYNC_OP_FAULT_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - The bit is used to enable interrupt by preload configurations fault."]
58    #[inline(always)]
59    pub fn dcache_preload_op_fault(&self) -> DCACHE_PRELOAD_OP_FAULT_R {
60        DCACHE_PRELOAD_OP_FAULT_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - The bit is used to enable interrupt by dcache trying to write flash."]
63    #[inline(always)]
64    pub fn dcache_write_flash(&self) -> DCACHE_WRITE_FLASH_R {
65        DCACHE_WRITE_FLASH_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
68    #[inline(always)]
69    pub fn mmu_entry_fault(&self) -> MMU_ENTRY_FAULT_R {
70        MMU_ENTRY_FAULT_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
73    #[inline(always)]
74    pub fn dcache_occupy_exc(&self) -> DCACHE_OCCUPY_EXC_R {
75        DCACHE_OCCUPY_EXC_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
78    #[inline(always)]
79    pub fn ibus_cnt_ovf(&self) -> IBUS_CNT_OVF_R {
80        IBUS_CNT_OVF_R::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
83    #[inline(always)]
84    pub fn dbus_cnt_ovf(&self) -> DBUS_CNT_OVF_R {
85        DBUS_CNT_OVF_R::new(((self.bits >> 8) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("CACHE_ILG_INT_ENA")
92            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
93            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
94            .field("dcache_sync_op_fault", &self.dcache_sync_op_fault())
95            .field("dcache_preload_op_fault", &self.dcache_preload_op_fault())
96            .field("dcache_write_flash", &self.dcache_write_flash())
97            .field("mmu_entry_fault", &self.mmu_entry_fault())
98            .field("dcache_occupy_exc", &self.dcache_occupy_exc())
99            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
100            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
106    #[inline(always)]
107    pub fn icache_sync_op_fault(&mut self) -> ICACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
108        ICACHE_SYNC_OP_FAULT_W::new(self, 0)
109    }
110    #[doc = "Bit 1 - The bit is used to enable interrupt by preload configurations fault."]
111    #[inline(always)]
112    pub fn icache_preload_op_fault(&mut self) -> ICACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
113        ICACHE_PRELOAD_OP_FAULT_W::new(self, 1)
114    }
115    #[doc = "Bit 2 - The bit is used to enable interrupt by sync configurations fault."]
116    #[inline(always)]
117    pub fn dcache_sync_op_fault(&mut self) -> DCACHE_SYNC_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
118        DCACHE_SYNC_OP_FAULT_W::new(self, 2)
119    }
120    #[doc = "Bit 3 - The bit is used to enable interrupt by preload configurations fault."]
121    #[inline(always)]
122    pub fn dcache_preload_op_fault(&mut self) -> DCACHE_PRELOAD_OP_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
123        DCACHE_PRELOAD_OP_FAULT_W::new(self, 3)
124    }
125    #[doc = "Bit 4 - The bit is used to enable interrupt by dcache trying to write flash."]
126    #[inline(always)]
127    pub fn dcache_write_flash(&mut self) -> DCACHE_WRITE_FLASH_W<CACHE_ILG_INT_ENA_SPEC> {
128        DCACHE_WRITE_FLASH_W::new(self, 4)
129    }
130    #[doc = "Bit 5 - The bit is used to enable interrupt by mmu entry fault."]
131    #[inline(always)]
132    pub fn mmu_entry_fault(&mut self) -> MMU_ENTRY_FAULT_W<CACHE_ILG_INT_ENA_SPEC> {
133        MMU_ENTRY_FAULT_W::new(self, 5)
134    }
135    #[doc = "Bit 6 - The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode."]
136    #[inline(always)]
137    pub fn dcache_occupy_exc(&mut self) -> DCACHE_OCCUPY_EXC_W<CACHE_ILG_INT_ENA_SPEC> {
138        DCACHE_OCCUPY_EXC_W::new(self, 6)
139    }
140    #[doc = "Bit 7 - The bit is used to enable interrupt by ibus counter overflow."]
141    #[inline(always)]
142    pub fn ibus_cnt_ovf(&mut self) -> IBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
143        IBUS_CNT_OVF_W::new(self, 7)
144    }
145    #[doc = "Bit 8 - The bit is used to enable interrupt by dbus counter overflow."]
146    #[inline(always)]
147    pub fn dbus_cnt_ovf(&mut self) -> DBUS_CNT_OVF_W<CACHE_ILG_INT_ENA_SPEC> {
148        DBUS_CNT_OVF_W::new(self, 8)
149    }
150}
151#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_ilg_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_ilg_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct CACHE_ILG_INT_ENA_SPEC;
153impl crate::RegisterSpec for CACHE_ILG_INT_ENA_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`cache_ilg_int_ena::R`](R) reader structure"]
157impl crate::Readable for CACHE_ILG_INT_ENA_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`cache_ilg_int_ena::W`](W) writer structure"]
159impl crate::Writable for CACHE_ILG_INT_ENA_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets CACHE_ILG_INT_ENA to value 0"]
165impl crate::Resettable for CACHE_ILG_INT_ENA_SPEC {
166    const RESET_VALUE: u32 = 0;
167}
esp32s3/extmem/cache_ilg_int_ena.rs

esp32s3/extmem/
cache_ilg_int_ena.rs
