esp32s3/extmem/
cache_bridge_arbiter_ctrl.rs

1#[doc = "Register `CACHE_BRIDGE_ARBITER_CTRL` reader"]
2pub type R = crate::R<CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
3#[doc = "Register `CACHE_BRIDGE_ARBITER_CTRL` writer"]
4pub type W = crate::W<CACHE_BRIDGE_ARBITER_CTRL_SPEC>;
5#[doc = "Field `ALLOC_WB_HOLD_ARBITER` reader - Reserved"]
6pub type ALLOC_WB_HOLD_ARBITER_R = crate::BitReader;
7#[doc = "Field `ALLOC_WB_HOLD_ARBITER` writer - Reserved"]
8pub type ALLOC_WB_HOLD_ARBITER_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - Reserved"]
11    #[inline(always)]
12    pub fn alloc_wb_hold_arbiter(&self) -> ALLOC_WB_HOLD_ARBITER_R {
13        ALLOC_WB_HOLD_ARBITER_R::new((self.bits & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CACHE_BRIDGE_ARBITER_CTRL")
20            .field("alloc_wb_hold_arbiter", &self.alloc_wb_hold_arbiter())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bit 0 - Reserved"]
26    #[inline(always)]
27    pub fn alloc_wb_hold_arbiter(
28        &mut self,
29    ) -> ALLOC_WB_HOLD_ARBITER_W<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
30        ALLOC_WB_HOLD_ARBITER_W::new(self, 0)
31    }
32}
33#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_bridge_arbiter_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_bridge_arbiter_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
34pub struct CACHE_BRIDGE_ARBITER_CTRL_SPEC;
35impl crate::RegisterSpec for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
36    type Ux = u32;
37}
38#[doc = "`read()` method returns [`cache_bridge_arbiter_ctrl::R`](R) reader structure"]
39impl crate::Readable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {}
40#[doc = "`write(|w| ..)` method takes [`cache_bridge_arbiter_ctrl::W`](W) writer structure"]
41impl crate::Writable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
42    type Safety = crate::Unsafe;
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
45}
46#[doc = "`reset()` method sets CACHE_BRIDGE_ARBITER_CTRL to value 0"]
47impl crate::Resettable for CACHE_BRIDGE_ARBITER_CTRL_SPEC {
48    const RESET_VALUE: u32 = 0;
49}
esp32s3/extmem/cache_bridge_arbiter_ctrl.rs

esp32s3/extmem/
cache_bridge_arbiter_ctrl.rs
