esp32s3/dma/
misc_conf.rs

1#[doc = "Register `MISC_CONF` reader"]
2pub type R = crate::R<MISC_CONF_SPEC>;
3#[doc = "Register `MISC_CONF` writer"]
4pub type W = crate::W<MISC_CONF_SPEC>;
5#[doc = "Field `AHBM_RST_INTER` reader - Set this bit, then clear this bit to reset the internal ahb FSM."]
6pub type AHBM_RST_INTER_R = crate::BitReader;
7#[doc = "Field `AHBM_RST_INTER` writer - Set this bit, then clear this bit to reset the internal ahb FSM."]
8pub type AHBM_RST_INTER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `AHBM_RST_EXTER` reader - Set this bit, then clear this bit to reset the external ahb FSM."]
10pub type AHBM_RST_EXTER_R = crate::BitReader;
11#[doc = "Field `AHBM_RST_EXTER` writer - Set this bit, then clear this bit to reset the external ahb FSM."]
12pub type AHBM_RST_EXTER_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."]
14pub type ARB_PRI_DIS_R = crate::BitReader;
15#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."]
16pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
18pub type CLK_EN_R = crate::BitReader;
19#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
20pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
23    #[inline(always)]
24    pub fn ahbm_rst_inter(&self) -> AHBM_RST_INTER_R {
25        AHBM_RST_INTER_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Set this bit, then clear this bit to reset the external ahb FSM."]
28    #[inline(always)]
29    pub fn ahbm_rst_exter(&self) -> AHBM_RST_EXTER_R {
30        AHBM_RST_EXTER_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
33    #[inline(always)]
34    pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R {
35        ARB_PRI_DIS_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
38    #[inline(always)]
39    pub fn clk_en(&self) -> CLK_EN_R {
40        CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("MISC_CONF")
47            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
48            .field("ahbm_rst_exter", &self.ahbm_rst_exter())
49            .field("arb_pri_dis", &self.arb_pri_dis())
50            .field("clk_en", &self.clk_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
56    #[inline(always)]
57    pub fn ahbm_rst_inter(&mut self) -> AHBM_RST_INTER_W<MISC_CONF_SPEC> {
58        AHBM_RST_INTER_W::new(self, 0)
59    }
60    #[doc = "Bit 1 - Set this bit, then clear this bit to reset the external ahb FSM."]
61    #[inline(always)]
62    pub fn ahbm_rst_exter(&mut self) -> AHBM_RST_EXTER_W<MISC_CONF_SPEC> {
63        AHBM_RST_EXTER_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
66    #[inline(always)]
67    pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W<MISC_CONF_SPEC> {
68        ARB_PRI_DIS_W::new(self, 2)
69    }
70    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
71    #[inline(always)]
72    pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
73        CLK_EN_W::new(self, 4)
74    }
75}
76#[doc = "MISC register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct MISC_CONF_SPEC;
78impl crate::RegisterSpec for MISC_CONF_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"]
82impl crate::Readable for MISC_CONF_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"]
84impl crate::Writable for MISC_CONF_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets MISC_CONF to value 0"]
90impl crate::Resettable for MISC_CONF_SPEC {
91    const RESET_VALUE: u32 = 0;
92}
esp32s3/dma/misc_conf.rs

esp32s3/dma/
misc_conf.rs
