1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 core_0_montr_ena: CORE_0_MONTR_ENA,
6 core_0_intr_raw: CORE_0_INTR_RAW,
7 core_0_intr_ena: CORE_0_INTR_ENA,
8 core_0_intr_clr: CORE_0_INTR_CLR,
9 core_0_area_dram0_0_min: CORE_0_AREA_DRAM0_0_MIN,
10 core_0_area_dram0_0_max: CORE_0_AREA_DRAM0_0_MAX,
11 core_0_area_dram0_1_min: CORE_0_AREA_DRAM0_1_MIN,
12 core_0_area_dram0_1_max: CORE_0_AREA_DRAM0_1_MAX,
13 core_0_area_pif_0_min: CORE_0_AREA_PIF_0_MIN,
14 core_0_area_pif_0_max: CORE_0_AREA_PIF_0_MAX,
15 core_0_area_pif_1_min: CORE_0_AREA_PIF_1_MIN,
16 core_0_area_pif_1_max: CORE_0_AREA_PIF_1_MAX,
17 core_0_area_sp: CORE_0_AREA_SP,
18 core_0_area_pc: CORE_0_AREA_PC,
19 core_0_sp_unstable: CORE_0_SP_UNSTABLE,
20 core_0_sp_min: CORE_0_SP_MIN,
21 core_0_sp_max: CORE_0_SP_MAX,
22 core_0_sp_pc: CORE_0_SP_PC,
23 core_0_rcd_pdebugenable: CORE_0_RCD_PDEBUGENABLE,
24 core_0_rcd_recording: CORE_0_RCD_RECORDING,
25 core_0_rcd_pdebuginst: CORE_0_RCD_PDEBUGINST,
26 core_0_rcd_pdebugstatus: CORE_0_RCD_PDEBUGSTATUS,
27 core_0_rcd_pdebugdata: CORE_0_RCD_PDEBUGDATA,
28 core_0_rcd_pdebugpc: CORE_0_RCD_PDEBUGPC,
29 core_0_rcd_pdebugls0stat: CORE_0_RCD_PDEBUGLS0STAT,
30 core_0_rcd_pdebugls0addr: CORE_0_RCD_PDEBUGLS0ADDR,
31 core_0_rcd_pdebugls0data: CORE_0_RCD_PDEBUGLS0DATA,
32 core_0_rcd_sp: CORE_0_RCD_SP,
33 core_0_iram0_exception_monitor_0: CORE_0_IRAM0_EXCEPTION_MONITOR_0,
34 core_0_iram0_exception_monitor_1: CORE_0_IRAM0_EXCEPTION_MONITOR_1,
35 core_0_dram0_exception_monitor_0: CORE_0_DRAM0_EXCEPTION_MONITOR_0,
36 core_0_dram0_exception_monitor_1: CORE_0_DRAM0_EXCEPTION_MONITOR_1,
37 core_0_dram0_exception_monitor_2: CORE_0_DRAM0_EXCEPTION_MONITOR_2,
38 core_0_dram0_exception_monitor_3: CORE_0_DRAM0_EXCEPTION_MONITOR_3,
39 core_0_dram0_exception_monitor_4: CORE_0_DRAM0_EXCEPTION_MONITOR_4,
40 core_0_dram0_exception_monitor_5: CORE_0_DRAM0_EXCEPTION_MONITOR_5,
41 core_1_montr_ena: CORE_1_MONTR_ENA,
42 core_1_intr_raw: CORE_1_INTR_RAW,
43 core_1_intr_ena: CORE_1_INTR_ENA,
44 core_1_intr_clr: CORE_1_INTR_CLR,
45 core_1_area_dram0_0_min: CORE_1_AREA_DRAM0_0_MIN,
46 core_1_area_dram0_0_max: CORE_1_AREA_DRAM0_0_MAX,
47 core_1_area_dram0_1_min: CORE_1_AREA_DRAM0_1_MIN,
48 core_1_area_dram0_1_max: CORE_1_AREA_DRAM0_1_MAX,
49 core_1_area_pif_0_min: CORE_1_AREA_PIF_0_MIN,
50 core_1_area_pif_0_max: CORE_1_AREA_PIF_0_MAX,
51 core_1_area_pif_1_min: CORE_1_AREA_PIF_1_MIN,
52 core_1_area_pif_1_max: CORE_1_AREA_PIF_1_MAX,
53 core_1_area_pc: CORE_1_AREA_PC,
54 core_1_area_sp: CORE_1_AREA_SP,
55 core_1_sp_unstable: CORE_1_SP_UNSTABLE,
56 core_1_sp_min: CORE_1_SP_MIN,
57 core_1_sp_max: CORE_1_SP_MAX,
58 core_1_sp_pc: CORE_1_SP_PC,
59 core_1_rcd_pdebugenable: CORE_1_RCD_PDEBUGENABLE,
60 core_1_rcd_recording: CORE_1_RCD_RECORDING,
61 core_1_rcd_pdebuginst: CORE_1_RCD_PDEBUGINST,
62 core_1_rcd_pdebugstatus: CORE_1_RCD_PDEBUGSTATUS,
63 core_1_rcd_pdebugdata: CORE_1_RCD_PDEBUGDATA,
64 core_1_rcd_pdebugpc: CORE_1_RCD_PDEBUGPC,
65 core_1_rcd_pdebugls0stat: CORE_1_RCD_PDEBUGLS0STAT,
66 core_1_rcd_pdebugls0addr: CORE_1_RCD_PDEBUGLS0ADDR,
67 core_1_rcd_pdebugls0data: CORE_1_RCD_PDEBUGLS0DATA,
68 core_1_rcd_sp: CORE_1_RCD_SP,
69 core_1_iram0_exception_monitor_0: CORE_1_IRAM0_EXCEPTION_MONITOR_0,
70 core_1_iram0_exception_monitor_1: CORE_1_IRAM0_EXCEPTION_MONITOR_1,
71 core_1_dram0_exception_monitor_0: CORE_1_DRAM0_EXCEPTION_MONITOR_0,
72 core_1_dram0_exception_monitor_1: CORE_1_DRAM0_EXCEPTION_MONITOR_1,
73 core_1_dram0_exception_monitor_2: CORE_1_DRAM0_EXCEPTION_MONITOR_2,
74 core_1_dram0_exception_monitor_3: CORE_1_DRAM0_EXCEPTION_MONITOR_3,
75 core_1_dram0_exception_monitor_4: CORE_1_DRAM0_EXCEPTION_MONITOR_4,
76 core_1_dram0_exception_monitor_5: CORE_1_DRAM0_EXCEPTION_MONITOR_5,
77 core_x_iram0_dram0_exception_monitor_0: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0,
78 core_x_iram0_dram0_exception_monitor_1: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1,
79 log_setting: LOG_SETTING,
80 log_data_0: LOG_DATA_0,
81 log_data_1: LOG_DATA_1,
82 log_data_2: LOG_DATA_2,
83 log_data_3: LOG_DATA_3,
84 log_data_mask: LOG_DATA_MASK,
85 log_min: LOG_MIN,
86 log_max: LOG_MAX,
87 log_mem_start: LOG_MEM_START,
88 log_mem_end: LOG_MEM_END,
89 log_mem_writing_addr: LOG_MEM_WRITING_ADDR,
90 log_mem_full_flag: LOG_MEM_FULL_FLAG,
91 _reserved86: [u8; 0xa4],
92 date: DATE,
93}
94impl RegisterBlock {
95 #[doc = "0x00 - core0 monitor enable configuration register"]
96 #[inline(always)]
97 pub const fn core_0_montr_ena(&self) -> &CORE_0_MONTR_ENA {
98 &self.core_0_montr_ena
99 }
100 #[doc = "0x04 - core0 monitor interrupt status register"]
101 #[inline(always)]
102 pub const fn core_0_intr_raw(&self) -> &CORE_0_INTR_RAW {
103 &self.core_0_intr_raw
104 }
105 #[doc = "0x08 - core0 monitor interrupt enable register"]
106 #[inline(always)]
107 pub const fn core_0_intr_ena(&self) -> &CORE_0_INTR_ENA {
108 &self.core_0_intr_ena
109 }
110 #[doc = "0x0c - core0 monitor interrupt clr register"]
111 #[inline(always)]
112 pub const fn core_0_intr_clr(&self) -> &CORE_0_INTR_CLR {
113 &self.core_0_intr_clr
114 }
115 #[doc = "0x10 - core0 dram0 region0 addr configuration register"]
116 #[inline(always)]
117 pub const fn core_0_area_dram0_0_min(&self) -> &CORE_0_AREA_DRAM0_0_MIN {
118 &self.core_0_area_dram0_0_min
119 }
120 #[doc = "0x14 - core0 dram0 region0 addr configuration register"]
121 #[inline(always)]
122 pub const fn core_0_area_dram0_0_max(&self) -> &CORE_0_AREA_DRAM0_0_MAX {
123 &self.core_0_area_dram0_0_max
124 }
125 #[doc = "0x18 - core0 dram0 region1 addr configuration register"]
126 #[inline(always)]
127 pub const fn core_0_area_dram0_1_min(&self) -> &CORE_0_AREA_DRAM0_1_MIN {
128 &self.core_0_area_dram0_1_min
129 }
130 #[doc = "0x1c - core0 dram0 region1 addr configuration register"]
131 #[inline(always)]
132 pub const fn core_0_area_dram0_1_max(&self) -> &CORE_0_AREA_DRAM0_1_MAX {
133 &self.core_0_area_dram0_1_max
134 }
135 #[doc = "0x20 - core0 PIF region0 addr configuration register"]
136 #[inline(always)]
137 pub const fn core_0_area_pif_0_min(&self) -> &CORE_0_AREA_PIF_0_MIN {
138 &self.core_0_area_pif_0_min
139 }
140 #[doc = "0x24 - core0 PIF region0 addr configuration register"]
141 #[inline(always)]
142 pub const fn core_0_area_pif_0_max(&self) -> &CORE_0_AREA_PIF_0_MAX {
143 &self.core_0_area_pif_0_max
144 }
145 #[doc = "0x28 - core0 PIF region1 addr configuration register"]
146 #[inline(always)]
147 pub const fn core_0_area_pif_1_min(&self) -> &CORE_0_AREA_PIF_1_MIN {
148 &self.core_0_area_pif_1_min
149 }
150 #[doc = "0x2c - core0 PIF region1 addr configuration register"]
151 #[inline(always)]
152 pub const fn core_0_area_pif_1_max(&self) -> &CORE_0_AREA_PIF_1_MAX {
153 &self.core_0_area_pif_1_max
154 }
155 #[doc = "0x30 - core0 area sp status register"]
156 #[inline(always)]
157 pub const fn core_0_area_sp(&self) -> &CORE_0_AREA_SP {
158 &self.core_0_area_sp
159 }
160 #[doc = "0x34 - core0 area pc status register"]
161 #[inline(always)]
162 pub const fn core_0_area_pc(&self) -> &CORE_0_AREA_PC {
163 &self.core_0_area_pc
164 }
165 #[doc = "0x38 - core0 sp unstable configuration register"]
166 #[inline(always)]
167 pub const fn core_0_sp_unstable(&self) -> &CORE_0_SP_UNSTABLE {
168 &self.core_0_sp_unstable
169 }
170 #[doc = "0x3c - core0 sp region configuration regsiter"]
171 #[inline(always)]
172 pub const fn core_0_sp_min(&self) -> &CORE_0_SP_MIN {
173 &self.core_0_sp_min
174 }
175 #[doc = "0x40 - core0 sp region configuration regsiter"]
176 #[inline(always)]
177 pub const fn core_0_sp_max(&self) -> &CORE_0_SP_MAX {
178 &self.core_0_sp_max
179 }
180 #[doc = "0x44 - core0 sp pc status register"]
181 #[inline(always)]
182 pub const fn core_0_sp_pc(&self) -> &CORE_0_SP_PC {
183 &self.core_0_sp_pc
184 }
185 #[doc = "0x48 - core0 pdebug configuration register"]
186 #[inline(always)]
187 pub const fn core_0_rcd_pdebugenable(&self) -> &CORE_0_RCD_PDEBUGENABLE {
188 &self.core_0_rcd_pdebugenable
189 }
190 #[doc = "0x4c - core0 pdebug status register"]
191 #[inline(always)]
192 pub const fn core_0_rcd_recording(&self) -> &CORE_0_RCD_RECORDING {
193 &self.core_0_rcd_recording
194 }
195 #[doc = "0x50 - core0 pdebug status register"]
196 #[inline(always)]
197 pub const fn core_0_rcd_pdebuginst(&self) -> &CORE_0_RCD_PDEBUGINST {
198 &self.core_0_rcd_pdebuginst
199 }
200 #[doc = "0x54 - core0 pdebug status register"]
201 #[inline(always)]
202 pub const fn core_0_rcd_pdebugstatus(&self) -> &CORE_0_RCD_PDEBUGSTATUS {
203 &self.core_0_rcd_pdebugstatus
204 }
205 #[doc = "0x58 - core0 pdebug status register"]
206 #[inline(always)]
207 pub const fn core_0_rcd_pdebugdata(&self) -> &CORE_0_RCD_PDEBUGDATA {
208 &self.core_0_rcd_pdebugdata
209 }
210 #[doc = "0x5c - core0 pdebug status register"]
211 #[inline(always)]
212 pub const fn core_0_rcd_pdebugpc(&self) -> &CORE_0_RCD_PDEBUGPC {
213 &self.core_0_rcd_pdebugpc
214 }
215 #[doc = "0x60 - core0 pdebug status register"]
216 #[inline(always)]
217 pub const fn core_0_rcd_pdebugls0stat(&self) -> &CORE_0_RCD_PDEBUGLS0STAT {
218 &self.core_0_rcd_pdebugls0stat
219 }
220 #[doc = "0x64 - core0 pdebug status register"]
221 #[inline(always)]
222 pub const fn core_0_rcd_pdebugls0addr(&self) -> &CORE_0_RCD_PDEBUGLS0ADDR {
223 &self.core_0_rcd_pdebugls0addr
224 }
225 #[doc = "0x68 - core0 pdebug status register"]
226 #[inline(always)]
227 pub const fn core_0_rcd_pdebugls0data(&self) -> &CORE_0_RCD_PDEBUGLS0DATA {
228 &self.core_0_rcd_pdebugls0data
229 }
230 #[doc = "0x6c - core0 pdebug status register"]
231 #[inline(always)]
232 pub const fn core_0_rcd_sp(&self) -> &CORE_0_RCD_SP {
233 &self.core_0_rcd_sp
234 }
235 #[doc = "0x70 - core0 bus busy status regsiter"]
236 #[inline(always)]
237 pub const fn core_0_iram0_exception_monitor_0(&self) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_0 {
238 &self.core_0_iram0_exception_monitor_0
239 }
240 #[doc = "0x74 - core0 bus busy status regsiter"]
241 #[inline(always)]
242 pub const fn core_0_iram0_exception_monitor_1(&self) -> &CORE_0_IRAM0_EXCEPTION_MONITOR_1 {
243 &self.core_0_iram0_exception_monitor_1
244 }
245 #[doc = "0x78 - core0 bus busy status regsiter"]
246 #[inline(always)]
247 pub const fn core_0_dram0_exception_monitor_0(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_0 {
248 &self.core_0_dram0_exception_monitor_0
249 }
250 #[doc = "0x7c - core0 bus busy status regsiter"]
251 #[inline(always)]
252 pub const fn core_0_dram0_exception_monitor_1(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_1 {
253 &self.core_0_dram0_exception_monitor_1
254 }
255 #[doc = "0x80 - core0 bus busy status regsiter"]
256 #[inline(always)]
257 pub const fn core_0_dram0_exception_monitor_2(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_2 {
258 &self.core_0_dram0_exception_monitor_2
259 }
260 #[doc = "0x84 - core0 bus busy status regsiter"]
261 #[inline(always)]
262 pub const fn core_0_dram0_exception_monitor_3(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_3 {
263 &self.core_0_dram0_exception_monitor_3
264 }
265 #[doc = "0x88 - core0 bus busy configuration regsiter"]
266 #[inline(always)]
267 pub const fn core_0_dram0_exception_monitor_4(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_4 {
268 &self.core_0_dram0_exception_monitor_4
269 }
270 #[doc = "0x8c - core0 bus busy configuration regsiter"]
271 #[inline(always)]
272 pub const fn core_0_dram0_exception_monitor_5(&self) -> &CORE_0_DRAM0_EXCEPTION_MONITOR_5 {
273 &self.core_0_dram0_exception_monitor_5
274 }
275 #[doc = "0x90 - Core1 monitor enable configuration register"]
276 #[inline(always)]
277 pub const fn core_1_montr_ena(&self) -> &CORE_1_MONTR_ENA {
278 &self.core_1_montr_ena
279 }
280 #[doc = "0x94 - Core1 monitor interrupt status register"]
281 #[inline(always)]
282 pub const fn core_1_intr_raw(&self) -> &CORE_1_INTR_RAW {
283 &self.core_1_intr_raw
284 }
285 #[doc = "0x98 - Core1 monitor interrupt enable register"]
286 #[inline(always)]
287 pub const fn core_1_intr_ena(&self) -> &CORE_1_INTR_ENA {
288 &self.core_1_intr_ena
289 }
290 #[doc = "0x9c - Core1 monitor interrupt clr register"]
291 #[inline(always)]
292 pub const fn core_1_intr_clr(&self) -> &CORE_1_INTR_CLR {
293 &self.core_1_intr_clr
294 }
295 #[doc = "0xa0 - Core1 dram0 region0 addr configuration register"]
296 #[inline(always)]
297 pub const fn core_1_area_dram0_0_min(&self) -> &CORE_1_AREA_DRAM0_0_MIN {
298 &self.core_1_area_dram0_0_min
299 }
300 #[doc = "0xa4 - Core1 dram0 region0 addr configuration register"]
301 #[inline(always)]
302 pub const fn core_1_area_dram0_0_max(&self) -> &CORE_1_AREA_DRAM0_0_MAX {
303 &self.core_1_area_dram0_0_max
304 }
305 #[doc = "0xa8 - Core1 dram0 region1 addr configuration register"]
306 #[inline(always)]
307 pub const fn core_1_area_dram0_1_min(&self) -> &CORE_1_AREA_DRAM0_1_MIN {
308 &self.core_1_area_dram0_1_min
309 }
310 #[doc = "0xac - Core1 dram0 region1 addr configuration register"]
311 #[inline(always)]
312 pub const fn core_1_area_dram0_1_max(&self) -> &CORE_1_AREA_DRAM0_1_MAX {
313 &self.core_1_area_dram0_1_max
314 }
315 #[doc = "0xb0 - Core1 PIF region0 addr configuration register"]
316 #[inline(always)]
317 pub const fn core_1_area_pif_0_min(&self) -> &CORE_1_AREA_PIF_0_MIN {
318 &self.core_1_area_pif_0_min
319 }
320 #[doc = "0xb4 - Core1 PIF region0 addr configuration register"]
321 #[inline(always)]
322 pub const fn core_1_area_pif_0_max(&self) -> &CORE_1_AREA_PIF_0_MAX {
323 &self.core_1_area_pif_0_max
324 }
325 #[doc = "0xb8 - Core1 PIF region1 addr configuration register"]
326 #[inline(always)]
327 pub const fn core_1_area_pif_1_min(&self) -> &CORE_1_AREA_PIF_1_MIN {
328 &self.core_1_area_pif_1_min
329 }
330 #[doc = "0xbc - Core1 PIF region1 addr configuration register"]
331 #[inline(always)]
332 pub const fn core_1_area_pif_1_max(&self) -> &CORE_1_AREA_PIF_1_MAX {
333 &self.core_1_area_pif_1_max
334 }
335 #[doc = "0xc0 - Core1 area sp status register"]
336 #[inline(always)]
337 pub const fn core_1_area_pc(&self) -> &CORE_1_AREA_PC {
338 &self.core_1_area_pc
339 }
340 #[doc = "0xc4 - Core1 area pc status register"]
341 #[inline(always)]
342 pub const fn core_1_area_sp(&self) -> &CORE_1_AREA_SP {
343 &self.core_1_area_sp
344 }
345 #[doc = "0xc8 - Core1 sp unstable configuration register"]
346 #[inline(always)]
347 pub const fn core_1_sp_unstable(&self) -> &CORE_1_SP_UNSTABLE {
348 &self.core_1_sp_unstable
349 }
350 #[doc = "0xcc - Core1 sp region configuration regsiter"]
351 #[inline(always)]
352 pub const fn core_1_sp_min(&self) -> &CORE_1_SP_MIN {
353 &self.core_1_sp_min
354 }
355 #[doc = "0xd0 - Core1 sp region configuration regsiter"]
356 #[inline(always)]
357 pub const fn core_1_sp_max(&self) -> &CORE_1_SP_MAX {
358 &self.core_1_sp_max
359 }
360 #[doc = "0xd4 - Core1 sp pc status register"]
361 #[inline(always)]
362 pub const fn core_1_sp_pc(&self) -> &CORE_1_SP_PC {
363 &self.core_1_sp_pc
364 }
365 #[doc = "0xd8 - Core1 pdebug configuration register"]
366 #[inline(always)]
367 pub const fn core_1_rcd_pdebugenable(&self) -> &CORE_1_RCD_PDEBUGENABLE {
368 &self.core_1_rcd_pdebugenable
369 }
370 #[doc = "0xdc - Core1 pdebug status register"]
371 #[inline(always)]
372 pub const fn core_1_rcd_recording(&self) -> &CORE_1_RCD_RECORDING {
373 &self.core_1_rcd_recording
374 }
375 #[doc = "0xe0 - Core1 pdebug status register"]
376 #[inline(always)]
377 pub const fn core_1_rcd_pdebuginst(&self) -> &CORE_1_RCD_PDEBUGINST {
378 &self.core_1_rcd_pdebuginst
379 }
380 #[doc = "0xe4 - Core1 pdebug status register"]
381 #[inline(always)]
382 pub const fn core_1_rcd_pdebugstatus(&self) -> &CORE_1_RCD_PDEBUGSTATUS {
383 &self.core_1_rcd_pdebugstatus
384 }
385 #[doc = "0xe8 - Core1 pdebug status register"]
386 #[inline(always)]
387 pub const fn core_1_rcd_pdebugdata(&self) -> &CORE_1_RCD_PDEBUGDATA {
388 &self.core_1_rcd_pdebugdata
389 }
390 #[doc = "0xec - Core1 pdebug status register"]
391 #[inline(always)]
392 pub const fn core_1_rcd_pdebugpc(&self) -> &CORE_1_RCD_PDEBUGPC {
393 &self.core_1_rcd_pdebugpc
394 }
395 #[doc = "0xf0 - Core1 pdebug status register"]
396 #[inline(always)]
397 pub const fn core_1_rcd_pdebugls0stat(&self) -> &CORE_1_RCD_PDEBUGLS0STAT {
398 &self.core_1_rcd_pdebugls0stat
399 }
400 #[doc = "0xf4 - Core1 pdebug status register"]
401 #[inline(always)]
402 pub const fn core_1_rcd_pdebugls0addr(&self) -> &CORE_1_RCD_PDEBUGLS0ADDR {
403 &self.core_1_rcd_pdebugls0addr
404 }
405 #[doc = "0xf8 - Core1 pdebug status register"]
406 #[inline(always)]
407 pub const fn core_1_rcd_pdebugls0data(&self) -> &CORE_1_RCD_PDEBUGLS0DATA {
408 &self.core_1_rcd_pdebugls0data
409 }
410 #[doc = "0xfc - Core1 pdebug status register"]
411 #[inline(always)]
412 pub const fn core_1_rcd_sp(&self) -> &CORE_1_RCD_SP {
413 &self.core_1_rcd_sp
414 }
415 #[doc = "0x100 - Core1 bus busy status regsiter"]
416 #[inline(always)]
417 pub const fn core_1_iram0_exception_monitor_0(&self) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_0 {
418 &self.core_1_iram0_exception_monitor_0
419 }
420 #[doc = "0x104 - Core1 bus busy status regsiter"]
421 #[inline(always)]
422 pub const fn core_1_iram0_exception_monitor_1(&self) -> &CORE_1_IRAM0_EXCEPTION_MONITOR_1 {
423 &self.core_1_iram0_exception_monitor_1
424 }
425 #[doc = "0x108 - Core1 bus busy status regsiter"]
426 #[inline(always)]
427 pub const fn core_1_dram0_exception_monitor_0(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_0 {
428 &self.core_1_dram0_exception_monitor_0
429 }
430 #[doc = "0x10c - Core1 bus busy status regsiter"]
431 #[inline(always)]
432 pub const fn core_1_dram0_exception_monitor_1(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_1 {
433 &self.core_1_dram0_exception_monitor_1
434 }
435 #[doc = "0x110 - Core1 bus busy status regsiter"]
436 #[inline(always)]
437 pub const fn core_1_dram0_exception_monitor_2(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_2 {
438 &self.core_1_dram0_exception_monitor_2
439 }
440 #[doc = "0x114 - Core1 bus busy status regsiter"]
441 #[inline(always)]
442 pub const fn core_1_dram0_exception_monitor_3(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_3 {
443 &self.core_1_dram0_exception_monitor_3
444 }
445 #[doc = "0x118 - Core1 bus busy status regsiter"]
446 #[inline(always)]
447 pub const fn core_1_dram0_exception_monitor_4(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_4 {
448 &self.core_1_dram0_exception_monitor_4
449 }
450 #[doc = "0x11c - Core1 bus busy status regsiter"]
451 #[inline(always)]
452 pub const fn core_1_dram0_exception_monitor_5(&self) -> &CORE_1_DRAM0_EXCEPTION_MONITOR_5 {
453 &self.core_1_dram0_exception_monitor_5
454 }
455 #[doc = "0x120 - bus busy configuration register"]
456 #[inline(always)]
457 pub const fn core_x_iram0_dram0_exception_monitor_0(
458 &self,
459 ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 {
460 &self.core_x_iram0_dram0_exception_monitor_0
461 }
462 #[doc = "0x124 - bus busy configuration register"]
463 #[inline(always)]
464 pub const fn core_x_iram0_dram0_exception_monitor_1(
465 &self,
466 ) -> &CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 {
467 &self.core_x_iram0_dram0_exception_monitor_1
468 }
469 #[doc = "0x128 - log set register"]
470 #[inline(always)]
471 pub const fn log_setting(&self) -> &LOG_SETTING {
472 &self.log_setting
473 }
474 #[doc = "0x12c - log check data register"]
475 #[inline(always)]
476 pub const fn log_data_0(&self) -> &LOG_DATA_0 {
477 &self.log_data_0
478 }
479 #[doc = "0x130 - log check data register"]
480 #[inline(always)]
481 pub const fn log_data_1(&self) -> &LOG_DATA_1 {
482 &self.log_data_1
483 }
484 #[doc = "0x134 - log check data register"]
485 #[inline(always)]
486 pub const fn log_data_2(&self) -> &LOG_DATA_2 {
487 &self.log_data_2
488 }
489 #[doc = "0x138 - log check data register"]
490 #[inline(always)]
491 pub const fn log_data_3(&self) -> &LOG_DATA_3 {
492 &self.log_data_3
493 }
494 #[doc = "0x13c - log check data mask register"]
495 #[inline(always)]
496 pub const fn log_data_mask(&self) -> &LOG_DATA_MASK {
497 &self.log_data_mask
498 }
499 #[doc = "0x140 - log check region configuration register"]
500 #[inline(always)]
501 pub const fn log_min(&self) -> &LOG_MIN {
502 &self.log_min
503 }
504 #[doc = "0x144 - log check region configuration register"]
505 #[inline(always)]
506 pub const fn log_max(&self) -> &LOG_MAX {
507 &self.log_max
508 }
509 #[doc = "0x148 - log mem region configuration register"]
510 #[inline(always)]
511 pub const fn log_mem_start(&self) -> &LOG_MEM_START {
512 &self.log_mem_start
513 }
514 #[doc = "0x14c - log mem region configuration register"]
515 #[inline(always)]
516 pub const fn log_mem_end(&self) -> &LOG_MEM_END {
517 &self.log_mem_end
518 }
519 #[doc = "0x150 - log mem addr status register"]
520 #[inline(always)]
521 pub const fn log_mem_writing_addr(&self) -> &LOG_MEM_WRITING_ADDR {
522 &self.log_mem_writing_addr
523 }
524 #[doc = "0x154 - log mem status register"]
525 #[inline(always)]
526 pub const fn log_mem_full_flag(&self) -> &LOG_MEM_FULL_FLAG {
527 &self.log_mem_full_flag
528 }
529 #[doc = "0x1fc - version register"]
530 #[inline(always)]
531 pub const fn date(&self) -> &DATE {
532 &self.date
533 }
534}
535#[doc = "CORE_0_MONTR_ENA (rw) register accessor: core0 monitor enable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_montr_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_montr_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_montr_ena`] module"]
536pub type CORE_0_MONTR_ENA = crate::Reg<core_0_montr_ena::CORE_0_MONTR_ENA_SPEC>;
537#[doc = "core0 monitor enable configuration register"]
538pub mod core_0_montr_ena;
539#[doc = "CORE_0_INTR_RAW (r) register accessor: core0 monitor interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_raw`] module"]
540pub type CORE_0_INTR_RAW = crate::Reg<core_0_intr_raw::CORE_0_INTR_RAW_SPEC>;
541#[doc = "core0 monitor interrupt status register"]
542pub mod core_0_intr_raw;
543#[doc = "CORE_0_INTR_ENA (rw) register accessor: core0 monitor interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_ena`] module"]
544pub type CORE_0_INTR_ENA = crate::Reg<core_0_intr_ena::CORE_0_INTR_ENA_SPEC>;
545#[doc = "core0 monitor interrupt enable register"]
546pub mod core_0_intr_ena;
547#[doc = "CORE_0_INTR_CLR (rw) register accessor: core0 monitor interrupt clr register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_intr_clr`] module"]
548pub type CORE_0_INTR_CLR = crate::Reg<core_0_intr_clr::CORE_0_INTR_CLR_SPEC>;
549#[doc = "core0 monitor interrupt clr register"]
550pub mod core_0_intr_clr;
551#[doc = "CORE_0_AREA_DRAM0_0_MIN (rw) register accessor: core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_0_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_0_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_0_min`] module"]
552pub type CORE_0_AREA_DRAM0_0_MIN =
553 crate::Reg<core_0_area_dram0_0_min::CORE_0_AREA_DRAM0_0_MIN_SPEC>;
554#[doc = "core0 dram0 region0 addr configuration register"]
555pub mod core_0_area_dram0_0_min;
556#[doc = "CORE_0_AREA_DRAM0_0_MAX (rw) register accessor: core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_0_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_0_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_0_max`] module"]
557pub type CORE_0_AREA_DRAM0_0_MAX =
558 crate::Reg<core_0_area_dram0_0_max::CORE_0_AREA_DRAM0_0_MAX_SPEC>;
559#[doc = "core0 dram0 region0 addr configuration register"]
560pub mod core_0_area_dram0_0_max;
561#[doc = "CORE_0_AREA_DRAM0_1_MIN (rw) register accessor: core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_1_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_1_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_1_min`] module"]
562pub type CORE_0_AREA_DRAM0_1_MIN =
563 crate::Reg<core_0_area_dram0_1_min::CORE_0_AREA_DRAM0_1_MIN_SPEC>;
564#[doc = "core0 dram0 region1 addr configuration register"]
565pub mod core_0_area_dram0_1_min;
566#[doc = "CORE_0_AREA_DRAM0_1_MAX (rw) register accessor: core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_1_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_1_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_dram0_1_max`] module"]
567pub type CORE_0_AREA_DRAM0_1_MAX =
568 crate::Reg<core_0_area_dram0_1_max::CORE_0_AREA_DRAM0_1_MAX_SPEC>;
569#[doc = "core0 dram0 region1 addr configuration register"]
570pub mod core_0_area_dram0_1_max;
571#[doc = "CORE_0_AREA_PIF_0_MIN (rw) register accessor: core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_0_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_0_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_0_min`] module"]
572pub type CORE_0_AREA_PIF_0_MIN = crate::Reg<core_0_area_pif_0_min::CORE_0_AREA_PIF_0_MIN_SPEC>;
573#[doc = "core0 PIF region0 addr configuration register"]
574pub mod core_0_area_pif_0_min;
575#[doc = "CORE_0_AREA_PIF_0_MAX (rw) register accessor: core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_0_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_0_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_0_max`] module"]
576pub type CORE_0_AREA_PIF_0_MAX = crate::Reg<core_0_area_pif_0_max::CORE_0_AREA_PIF_0_MAX_SPEC>;
577#[doc = "core0 PIF region0 addr configuration register"]
578pub mod core_0_area_pif_0_max;
579#[doc = "CORE_0_AREA_PIF_1_MIN (rw) register accessor: core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_1_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_1_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_1_min`] module"]
580pub type CORE_0_AREA_PIF_1_MIN = crate::Reg<core_0_area_pif_1_min::CORE_0_AREA_PIF_1_MIN_SPEC>;
581#[doc = "core0 PIF region1 addr configuration register"]
582pub mod core_0_area_pif_1_min;
583#[doc = "CORE_0_AREA_PIF_1_MAX (rw) register accessor: core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_1_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_1_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pif_1_max`] module"]
584pub type CORE_0_AREA_PIF_1_MAX = crate::Reg<core_0_area_pif_1_max::CORE_0_AREA_PIF_1_MAX_SPEC>;
585#[doc = "core0 PIF region1 addr configuration register"]
586pub mod core_0_area_pif_1_max;
587#[doc = "CORE_0_AREA_SP (r) register accessor: core0 area sp status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_sp`] module"]
588pub type CORE_0_AREA_SP = crate::Reg<core_0_area_sp::CORE_0_AREA_SP_SPEC>;
589#[doc = "core0 area sp status register"]
590pub mod core_0_area_sp;
591#[doc = "CORE_0_AREA_PC (r) register accessor: core0 area pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_area_pc`] module"]
592pub type CORE_0_AREA_PC = crate::Reg<core_0_area_pc::CORE_0_AREA_PC_SPEC>;
593#[doc = "core0 area pc status register"]
594pub mod core_0_area_pc;
595#[doc = "CORE_0_SP_UNSTABLE (rw) register accessor: core0 sp unstable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_unstable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_unstable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_unstable`] module"]
596pub type CORE_0_SP_UNSTABLE = crate::Reg<core_0_sp_unstable::CORE_0_SP_UNSTABLE_SPEC>;
597#[doc = "core0 sp unstable configuration register"]
598pub mod core_0_sp_unstable;
599#[doc = "CORE_0_SP_MIN (rw) register accessor: core0 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_min`] module"]
600pub type CORE_0_SP_MIN = crate::Reg<core_0_sp_min::CORE_0_SP_MIN_SPEC>;
601#[doc = "core0 sp region configuration regsiter"]
602pub mod core_0_sp_min;
603#[doc = "CORE_0_SP_MAX (rw) register accessor: core0 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_max`] module"]
604pub type CORE_0_SP_MAX = crate::Reg<core_0_sp_max::CORE_0_SP_MAX_SPEC>;
605#[doc = "core0 sp region configuration regsiter"]
606pub mod core_0_sp_max;
607#[doc = "CORE_0_SP_PC (r) register accessor: core0 sp pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_sp_pc`] module"]
608pub type CORE_0_SP_PC = crate::Reg<core_0_sp_pc::CORE_0_SP_PC_SPEC>;
609#[doc = "core0 sp pc status register"]
610pub mod core_0_sp_pc;
611#[doc = "CORE_0_RCD_PDEBUGENABLE (rw) register accessor: core0 pdebug configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_rcd_pdebugenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugenable`] module"]
612pub type CORE_0_RCD_PDEBUGENABLE =
613 crate::Reg<core_0_rcd_pdebugenable::CORE_0_RCD_PDEBUGENABLE_SPEC>;
614#[doc = "core0 pdebug configuration register"]
615pub mod core_0_rcd_pdebugenable;
616#[doc = "CORE_0_RCD_RECORDING (rw) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_recording::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_rcd_recording::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_recording`] module"]
617pub type CORE_0_RCD_RECORDING = crate::Reg<core_0_rcd_recording::CORE_0_RCD_RECORDING_SPEC>;
618#[doc = "core0 pdebug status register"]
619pub mod core_0_rcd_recording;
620#[doc = "CORE_0_RCD_PDEBUGINST (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebuginst::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebuginst`] module"]
621pub type CORE_0_RCD_PDEBUGINST = crate::Reg<core_0_rcd_pdebuginst::CORE_0_RCD_PDEBUGINST_SPEC>;
622#[doc = "core0 pdebug status register"]
623pub mod core_0_rcd_pdebuginst;
624#[doc = "CORE_0_RCD_PDEBUGSTATUS (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugstatus`] module"]
625pub type CORE_0_RCD_PDEBUGSTATUS =
626 crate::Reg<core_0_rcd_pdebugstatus::CORE_0_RCD_PDEBUGSTATUS_SPEC>;
627#[doc = "core0 pdebug status register"]
628pub mod core_0_rcd_pdebugstatus;
629#[doc = "CORE_0_RCD_PDEBUGDATA (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugdata`] module"]
630pub type CORE_0_RCD_PDEBUGDATA = crate::Reg<core_0_rcd_pdebugdata::CORE_0_RCD_PDEBUGDATA_SPEC>;
631#[doc = "core0 pdebug status register"]
632pub mod core_0_rcd_pdebugdata;
633#[doc = "CORE_0_RCD_PDEBUGPC (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugpc`] module"]
634pub type CORE_0_RCD_PDEBUGPC = crate::Reg<core_0_rcd_pdebugpc::CORE_0_RCD_PDEBUGPC_SPEC>;
635#[doc = "core0 pdebug status register"]
636pub mod core_0_rcd_pdebugpc;
637#[doc = "CORE_0_RCD_PDEBUGLS0STAT (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugls0stat`] module"]
638pub type CORE_0_RCD_PDEBUGLS0STAT =
639 crate::Reg<core_0_rcd_pdebugls0stat::CORE_0_RCD_PDEBUGLS0STAT_SPEC>;
640#[doc = "core0 pdebug status register"]
641pub mod core_0_rcd_pdebugls0stat;
642#[doc = "CORE_0_RCD_PDEBUGLS0ADDR (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugls0addr`] module"]
643pub type CORE_0_RCD_PDEBUGLS0ADDR =
644 crate::Reg<core_0_rcd_pdebugls0addr::CORE_0_RCD_PDEBUGLS0ADDR_SPEC>;
645#[doc = "core0 pdebug status register"]
646pub mod core_0_rcd_pdebugls0addr;
647#[doc = "CORE_0_RCD_PDEBUGLS0DATA (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_pdebugls0data`] module"]
648pub type CORE_0_RCD_PDEBUGLS0DATA =
649 crate::Reg<core_0_rcd_pdebugls0data::CORE_0_RCD_PDEBUGLS0DATA_SPEC>;
650#[doc = "core0 pdebug status register"]
651pub mod core_0_rcd_pdebugls0data;
652#[doc = "CORE_0_RCD_SP (r) register accessor: core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_rcd_sp`] module"]
653pub type CORE_0_RCD_SP = crate::Reg<core_0_rcd_sp::CORE_0_RCD_SP_SPEC>;
654#[doc = "core0 pdebug status register"]
655pub mod core_0_rcd_sp;
656#[doc = "CORE_0_IRAM0_EXCEPTION_MONITOR_0 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_iram0_exception_monitor_0`] module"]
657pub type CORE_0_IRAM0_EXCEPTION_MONITOR_0 =
658 crate::Reg<core_0_iram0_exception_monitor_0::CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC>;
659#[doc = "core0 bus busy status regsiter"]
660pub mod core_0_iram0_exception_monitor_0;
661#[doc = "CORE_0_IRAM0_EXCEPTION_MONITOR_1 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_iram0_exception_monitor_1`] module"]
662pub type CORE_0_IRAM0_EXCEPTION_MONITOR_1 =
663 crate::Reg<core_0_iram0_exception_monitor_1::CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC>;
664#[doc = "core0 bus busy status regsiter"]
665pub mod core_0_iram0_exception_monitor_1;
666#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_0 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_0`] module"]
667pub type CORE_0_DRAM0_EXCEPTION_MONITOR_0 =
668 crate::Reg<core_0_dram0_exception_monitor_0::CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
669#[doc = "core0 bus busy status regsiter"]
670pub mod core_0_dram0_exception_monitor_0;
671#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_1 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_1`] module"]
672pub type CORE_0_DRAM0_EXCEPTION_MONITOR_1 =
673 crate::Reg<core_0_dram0_exception_monitor_1::CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
674#[doc = "core0 bus busy status regsiter"]
675pub mod core_0_dram0_exception_monitor_1;
676#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_2 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_2`] module"]
677pub type CORE_0_DRAM0_EXCEPTION_MONITOR_2 =
678 crate::Reg<core_0_dram0_exception_monitor_2::CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC>;
679#[doc = "core0 bus busy status regsiter"]
680pub mod core_0_dram0_exception_monitor_2;
681#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_3 (r) register accessor: core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_3`] module"]
682pub type CORE_0_DRAM0_EXCEPTION_MONITOR_3 =
683 crate::Reg<core_0_dram0_exception_monitor_3::CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC>;
684#[doc = "core0 bus busy status regsiter"]
685pub mod core_0_dram0_exception_monitor_3;
686#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_4 (r) register accessor: core0 bus busy configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_4`] module"]
687pub type CORE_0_DRAM0_EXCEPTION_MONITOR_4 =
688 crate::Reg<core_0_dram0_exception_monitor_4::CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC>;
689#[doc = "core0 bus busy configuration regsiter"]
690pub mod core_0_dram0_exception_monitor_4;
691#[doc = "CORE_0_DRAM0_EXCEPTION_MONITOR_5 (r) register accessor: core0 bus busy configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_0_dram0_exception_monitor_5`] module"]
692pub type CORE_0_DRAM0_EXCEPTION_MONITOR_5 =
693 crate::Reg<core_0_dram0_exception_monitor_5::CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC>;
694#[doc = "core0 bus busy configuration regsiter"]
695pub mod core_0_dram0_exception_monitor_5;
696#[doc = "CORE_1_MONTR_ENA (rw) register accessor: Core1 monitor enable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_montr_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_montr_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_montr_ena`] module"]
697pub type CORE_1_MONTR_ENA = crate::Reg<core_1_montr_ena::CORE_1_MONTR_ENA_SPEC>;
698#[doc = "Core1 monitor enable configuration register"]
699pub mod core_1_montr_ena;
700#[doc = "CORE_1_INTR_RAW (r) register accessor: Core1 monitor interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_raw`] module"]
701pub type CORE_1_INTR_RAW = crate::Reg<core_1_intr_raw::CORE_1_INTR_RAW_SPEC>;
702#[doc = "Core1 monitor interrupt status register"]
703pub mod core_1_intr_raw;
704#[doc = "CORE_1_INTR_ENA (rw) register accessor: Core1 monitor interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_intr_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_ena`] module"]
705pub type CORE_1_INTR_ENA = crate::Reg<core_1_intr_ena::CORE_1_INTR_ENA_SPEC>;
706#[doc = "Core1 monitor interrupt enable register"]
707pub mod core_1_intr_ena;
708#[doc = "CORE_1_INTR_CLR (rw) register accessor: Core1 monitor interrupt clr register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_intr_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_intr_clr`] module"]
709pub type CORE_1_INTR_CLR = crate::Reg<core_1_intr_clr::CORE_1_INTR_CLR_SPEC>;
710#[doc = "Core1 monitor interrupt clr register"]
711pub mod core_1_intr_clr;
712#[doc = "CORE_1_AREA_DRAM0_0_MIN (rw) register accessor: Core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_0_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_0_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_0_min`] module"]
713pub type CORE_1_AREA_DRAM0_0_MIN =
714 crate::Reg<core_1_area_dram0_0_min::CORE_1_AREA_DRAM0_0_MIN_SPEC>;
715#[doc = "Core1 dram0 region0 addr configuration register"]
716pub mod core_1_area_dram0_0_min;
717#[doc = "CORE_1_AREA_DRAM0_0_MAX (rw) register accessor: Core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_0_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_0_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_0_max`] module"]
718pub type CORE_1_AREA_DRAM0_0_MAX =
719 crate::Reg<core_1_area_dram0_0_max::CORE_1_AREA_DRAM0_0_MAX_SPEC>;
720#[doc = "Core1 dram0 region0 addr configuration register"]
721pub mod core_1_area_dram0_0_max;
722#[doc = "CORE_1_AREA_DRAM0_1_MIN (rw) register accessor: Core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_1_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_1_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_1_min`] module"]
723pub type CORE_1_AREA_DRAM0_1_MIN =
724 crate::Reg<core_1_area_dram0_1_min::CORE_1_AREA_DRAM0_1_MIN_SPEC>;
725#[doc = "Core1 dram0 region1 addr configuration register"]
726pub mod core_1_area_dram0_1_min;
727#[doc = "CORE_1_AREA_DRAM0_1_MAX (rw) register accessor: Core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_1_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_1_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_dram0_1_max`] module"]
728pub type CORE_1_AREA_DRAM0_1_MAX =
729 crate::Reg<core_1_area_dram0_1_max::CORE_1_AREA_DRAM0_1_MAX_SPEC>;
730#[doc = "Core1 dram0 region1 addr configuration register"]
731pub mod core_1_area_dram0_1_max;
732#[doc = "CORE_1_AREA_PIF_0_MIN (rw) register accessor: Core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_0_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_0_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_0_min`] module"]
733pub type CORE_1_AREA_PIF_0_MIN = crate::Reg<core_1_area_pif_0_min::CORE_1_AREA_PIF_0_MIN_SPEC>;
734#[doc = "Core1 PIF region0 addr configuration register"]
735pub mod core_1_area_pif_0_min;
736#[doc = "CORE_1_AREA_PIF_0_MAX (rw) register accessor: Core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_0_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_0_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_0_max`] module"]
737pub type CORE_1_AREA_PIF_0_MAX = crate::Reg<core_1_area_pif_0_max::CORE_1_AREA_PIF_0_MAX_SPEC>;
738#[doc = "Core1 PIF region0 addr configuration register"]
739pub mod core_1_area_pif_0_max;
740#[doc = "CORE_1_AREA_PIF_1_MIN (rw) register accessor: Core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_1_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_1_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_1_min`] module"]
741pub type CORE_1_AREA_PIF_1_MIN = crate::Reg<core_1_area_pif_1_min::CORE_1_AREA_PIF_1_MIN_SPEC>;
742#[doc = "Core1 PIF region1 addr configuration register"]
743pub mod core_1_area_pif_1_min;
744#[doc = "CORE_1_AREA_PIF_1_MAX (rw) register accessor: Core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_1_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_1_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pif_1_max`] module"]
745pub type CORE_1_AREA_PIF_1_MAX = crate::Reg<core_1_area_pif_1_max::CORE_1_AREA_PIF_1_MAX_SPEC>;
746#[doc = "Core1 PIF region1 addr configuration register"]
747pub mod core_1_area_pif_1_max;
748#[doc = "CORE_1_AREA_PC (r) register accessor: Core1 area sp status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_pc`] module"]
749pub type CORE_1_AREA_PC = crate::Reg<core_1_area_pc::CORE_1_AREA_PC_SPEC>;
750#[doc = "Core1 area sp status register"]
751pub mod core_1_area_pc;
752#[doc = "CORE_1_AREA_SP (r) register accessor: Core1 area pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_area_sp`] module"]
753pub type CORE_1_AREA_SP = crate::Reg<core_1_area_sp::CORE_1_AREA_SP_SPEC>;
754#[doc = "Core1 area pc status register"]
755pub mod core_1_area_sp;
756#[doc = "CORE_1_SP_UNSTABLE (rw) register accessor: Core1 sp unstable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_unstable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_unstable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_unstable`] module"]
757pub type CORE_1_SP_UNSTABLE = crate::Reg<core_1_sp_unstable::CORE_1_SP_UNSTABLE_SPEC>;
758#[doc = "Core1 sp unstable configuration register"]
759pub mod core_1_sp_unstable;
760#[doc = "CORE_1_SP_MIN (rw) register accessor: Core1 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_min`] module"]
761pub type CORE_1_SP_MIN = crate::Reg<core_1_sp_min::CORE_1_SP_MIN_SPEC>;
762#[doc = "Core1 sp region configuration regsiter"]
763pub mod core_1_sp_min;
764#[doc = "CORE_1_SP_MAX (rw) register accessor: Core1 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_max`] module"]
765pub type CORE_1_SP_MAX = crate::Reg<core_1_sp_max::CORE_1_SP_MAX_SPEC>;
766#[doc = "Core1 sp region configuration regsiter"]
767pub mod core_1_sp_max;
768#[doc = "CORE_1_SP_PC (r) register accessor: Core1 sp pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_pc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_sp_pc`] module"]
769pub type CORE_1_SP_PC = crate::Reg<core_1_sp_pc::CORE_1_SP_PC_SPEC>;
770#[doc = "Core1 sp pc status register"]
771pub mod core_1_sp_pc;
772#[doc = "CORE_1_RCD_PDEBUGENABLE (rw) register accessor: Core1 pdebug configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugenable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_rcd_pdebugenable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugenable`] module"]
773pub type CORE_1_RCD_PDEBUGENABLE =
774 crate::Reg<core_1_rcd_pdebugenable::CORE_1_RCD_PDEBUGENABLE_SPEC>;
775#[doc = "Core1 pdebug configuration register"]
776pub mod core_1_rcd_pdebugenable;
777#[doc = "CORE_1_RCD_RECORDING (rw) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_recording::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_rcd_recording::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_recording`] module"]
778pub type CORE_1_RCD_RECORDING = crate::Reg<core_1_rcd_recording::CORE_1_RCD_RECORDING_SPEC>;
779#[doc = "Core1 pdebug status register"]
780pub mod core_1_rcd_recording;
781#[doc = "CORE_1_RCD_PDEBUGINST (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebuginst::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebuginst`] module"]
782pub type CORE_1_RCD_PDEBUGINST = crate::Reg<core_1_rcd_pdebuginst::CORE_1_RCD_PDEBUGINST_SPEC>;
783#[doc = "Core1 pdebug status register"]
784pub mod core_1_rcd_pdebuginst;
785#[doc = "CORE_1_RCD_PDEBUGSTATUS (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugstatus`] module"]
786pub type CORE_1_RCD_PDEBUGSTATUS =
787 crate::Reg<core_1_rcd_pdebugstatus::CORE_1_RCD_PDEBUGSTATUS_SPEC>;
788#[doc = "Core1 pdebug status register"]
789pub mod core_1_rcd_pdebugstatus;
790#[doc = "CORE_1_RCD_PDEBUGDATA (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugdata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugdata`] module"]
791pub type CORE_1_RCD_PDEBUGDATA = crate::Reg<core_1_rcd_pdebugdata::CORE_1_RCD_PDEBUGDATA_SPEC>;
792#[doc = "Core1 pdebug status register"]
793pub mod core_1_rcd_pdebugdata;
794#[doc = "CORE_1_RCD_PDEBUGPC (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugpc`] module"]
795pub type CORE_1_RCD_PDEBUGPC = crate::Reg<core_1_rcd_pdebugpc::CORE_1_RCD_PDEBUGPC_SPEC>;
796#[doc = "Core1 pdebug status register"]
797pub mod core_1_rcd_pdebugpc;
798#[doc = "CORE_1_RCD_PDEBUGLS0STAT (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugls0stat`] module"]
799pub type CORE_1_RCD_PDEBUGLS0STAT =
800 crate::Reg<core_1_rcd_pdebugls0stat::CORE_1_RCD_PDEBUGLS0STAT_SPEC>;
801#[doc = "Core1 pdebug status register"]
802pub mod core_1_rcd_pdebugls0stat;
803#[doc = "CORE_1_RCD_PDEBUGLS0ADDR (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugls0addr`] module"]
804pub type CORE_1_RCD_PDEBUGLS0ADDR =
805 crate::Reg<core_1_rcd_pdebugls0addr::CORE_1_RCD_PDEBUGLS0ADDR_SPEC>;
806#[doc = "Core1 pdebug status register"]
807pub mod core_1_rcd_pdebugls0addr;
808#[doc = "CORE_1_RCD_PDEBUGLS0DATA (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_pdebugls0data`] module"]
809pub type CORE_1_RCD_PDEBUGLS0DATA =
810 crate::Reg<core_1_rcd_pdebugls0data::CORE_1_RCD_PDEBUGLS0DATA_SPEC>;
811#[doc = "Core1 pdebug status register"]
812pub mod core_1_rcd_pdebugls0data;
813#[doc = "CORE_1_RCD_SP (r) register accessor: Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_sp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_rcd_sp`] module"]
814pub type CORE_1_RCD_SP = crate::Reg<core_1_rcd_sp::CORE_1_RCD_SP_SPEC>;
815#[doc = "Core1 pdebug status register"]
816pub mod core_1_rcd_sp;
817#[doc = "CORE_1_IRAM0_EXCEPTION_MONITOR_0 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_iram0_exception_monitor_0`] module"]
818pub type CORE_1_IRAM0_EXCEPTION_MONITOR_0 =
819 crate::Reg<core_1_iram0_exception_monitor_0::CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC>;
820#[doc = "Core1 bus busy status regsiter"]
821pub mod core_1_iram0_exception_monitor_0;
822#[doc = "CORE_1_IRAM0_EXCEPTION_MONITOR_1 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_iram0_exception_monitor_1`] module"]
823pub type CORE_1_IRAM0_EXCEPTION_MONITOR_1 =
824 crate::Reg<core_1_iram0_exception_monitor_1::CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC>;
825#[doc = "Core1 bus busy status regsiter"]
826pub mod core_1_iram0_exception_monitor_1;
827#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_0 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_0`] module"]
828pub type CORE_1_DRAM0_EXCEPTION_MONITOR_0 =
829 crate::Reg<core_1_dram0_exception_monitor_0::CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
830#[doc = "Core1 bus busy status regsiter"]
831pub mod core_1_dram0_exception_monitor_0;
832#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_1 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_1`] module"]
833pub type CORE_1_DRAM0_EXCEPTION_MONITOR_1 =
834 crate::Reg<core_1_dram0_exception_monitor_1::CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
835#[doc = "Core1 bus busy status regsiter"]
836pub mod core_1_dram0_exception_monitor_1;
837#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_2 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_2`] module"]
838pub type CORE_1_DRAM0_EXCEPTION_MONITOR_2 =
839 crate::Reg<core_1_dram0_exception_monitor_2::CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC>;
840#[doc = "Core1 bus busy status regsiter"]
841pub mod core_1_dram0_exception_monitor_2;
842#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_3 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_3`] module"]
843pub type CORE_1_DRAM0_EXCEPTION_MONITOR_3 =
844 crate::Reg<core_1_dram0_exception_monitor_3::CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC>;
845#[doc = "Core1 bus busy status regsiter"]
846pub mod core_1_dram0_exception_monitor_3;
847#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_4 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_4`] module"]
848pub type CORE_1_DRAM0_EXCEPTION_MONITOR_4 =
849 crate::Reg<core_1_dram0_exception_monitor_4::CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC>;
850#[doc = "Core1 bus busy status regsiter"]
851pub mod core_1_dram0_exception_monitor_4;
852#[doc = "CORE_1_DRAM0_EXCEPTION_MONITOR_5 (r) register accessor: Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_1_dram0_exception_monitor_5`] module"]
853pub type CORE_1_DRAM0_EXCEPTION_MONITOR_5 =
854 crate::Reg<core_1_dram0_exception_monitor_5::CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC>;
855#[doc = "Core1 bus busy status regsiter"]
856pub mod core_1_dram0_exception_monitor_5;
857#[doc = "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 (rw) register accessor: bus busy configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_x_iram0_dram0_exception_monitor_0`] module"]
858pub type CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 =
859 crate::Reg<core_x_iram0_dram0_exception_monitor_0::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
860#[doc = "bus busy configuration register"]
861pub mod core_x_iram0_dram0_exception_monitor_0;
862#[doc = "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 (rw) register accessor: bus busy configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@core_x_iram0_dram0_exception_monitor_1`] module"]
863pub type CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 =
864 crate::Reg<core_x_iram0_dram0_exception_monitor_1::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
865#[doc = "bus busy configuration register"]
866pub mod core_x_iram0_dram0_exception_monitor_1;
867#[doc = "LOG_SETTING (rw) register accessor: log set register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_setting::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_setting::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_setting`] module"]
868pub type LOG_SETTING = crate::Reg<log_setting::LOG_SETTING_SPEC>;
869#[doc = "log set register"]
870pub mod log_setting;
871#[doc = "LOG_DATA_0 (rw) register accessor: log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_data_0`] module"]
872pub type LOG_DATA_0 = crate::Reg<log_data_0::LOG_DATA_0_SPEC>;
873#[doc = "log check data register"]
874pub mod log_data_0;
875#[doc = "LOG_DATA_1 (rw) register accessor: log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_data_1`] module"]
876pub type LOG_DATA_1 = crate::Reg<log_data_1::LOG_DATA_1_SPEC>;
877#[doc = "log check data register"]
878pub mod log_data_1;
879#[doc = "LOG_DATA_2 (rw) register accessor: log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_data_2`] module"]
880pub type LOG_DATA_2 = crate::Reg<log_data_2::LOG_DATA_2_SPEC>;
881#[doc = "log check data register"]
882pub mod log_data_2;
883#[doc = "LOG_DATA_3 (rw) register accessor: log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_data_3`] module"]
884pub type LOG_DATA_3 = crate::Reg<log_data_3::LOG_DATA_3_SPEC>;
885#[doc = "log check data register"]
886pub mod log_data_3;
887#[doc = "LOG_DATA_MASK (rw) register accessor: log check data mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_data_mask`] module"]
888pub type LOG_DATA_MASK = crate::Reg<log_data_mask::LOG_DATA_MASK_SPEC>;
889#[doc = "log check data mask register"]
890pub mod log_data_mask;
891#[doc = "LOG_MIN (rw) register accessor: log check region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_min::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_min::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_min`] module"]
892pub type LOG_MIN = crate::Reg<log_min::LOG_MIN_SPEC>;
893#[doc = "log check region configuration register"]
894pub mod log_min;
895#[doc = "LOG_MAX (rw) register accessor: log check region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_max::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_max::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_max`] module"]
896pub type LOG_MAX = crate::Reg<log_max::LOG_MAX_SPEC>;
897#[doc = "log check region configuration register"]
898pub mod log_max;
899#[doc = "LOG_MEM_START (rw) register accessor: log mem region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_mem_start`] module"]
900pub type LOG_MEM_START = crate::Reg<log_mem_start::LOG_MEM_START_SPEC>;
901#[doc = "log mem region configuration register"]
902pub mod log_mem_start;
903#[doc = "LOG_MEM_END (rw) register accessor: log mem region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_mem_end`] module"]
904pub type LOG_MEM_END = crate::Reg<log_mem_end::LOG_MEM_END_SPEC>;
905#[doc = "log mem region configuration register"]
906pub mod log_mem_end;
907#[doc = "LOG_MEM_WRITING_ADDR (r) register accessor: log mem addr status register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_writing_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_mem_writing_addr`] module"]
908pub type LOG_MEM_WRITING_ADDR = crate::Reg<log_mem_writing_addr::LOG_MEM_WRITING_ADDR_SPEC>;
909#[doc = "log mem addr status register"]
910pub mod log_mem_writing_addr;
911#[doc = "LOG_MEM_FULL_FLAG (rw) register accessor: log mem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_full_flag::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_full_flag::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@log_mem_full_flag`] module"]
912pub type LOG_MEM_FULL_FLAG = crate::Reg<log_mem_full_flag::LOG_MEM_FULL_FLAG_SPEC>;
913#[doc = "log mem status register"]
914pub mod log_mem_full_flag;
915#[doc = "DATE (rw) register accessor: version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
916pub type DATE = crate::Reg<date::DATE_SPEC>;
917#[doc = "version register"]
918pub mod date;