esp32s3/sensitive/
core_1_dram0_pms_monitor_1.rs

1#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_1` reader"]
2pub type R = crate::R<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>;
3#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_1` writer"]
4pub type W = crate::W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>;
5#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear core1 dram0 permission monior interrupt."]
6pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
7#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear core1 dram0 permission monior interrupt."]
8pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable core1 dram0 permission monitor interrupt."]
10pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
11#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable core1 dram0 permission monitor interrupt."]
12pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
15    #[inline(always)]
16    pub fn core_1_dram0_pms_monitor_violate_clr(&self) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R {
17        CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bit 1 - Set 1 to enable core1 dram0 permission monitor interrupt."]
20    #[inline(always)]
21    pub fn core_1_dram0_pms_monitor_violate_en(&self) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R {
22        CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_1")
29            .field(
30                "core_1_dram0_pms_monitor_violate_clr",
31                &self.core_1_dram0_pms_monitor_violate_clr(),
32            )
33            .field(
34                "core_1_dram0_pms_monitor_violate_en",
35                &self.core_1_dram0_pms_monitor_violate_en(),
36            )
37            .finish()
38    }
39}
40impl W {
41    #[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
42    #[inline(always)]
43    pub fn core_1_dram0_pms_monitor_violate_clr(
44        &mut self,
45    ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
46        CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
47    }
48    #[doc = "Bit 1 - Set 1 to enable core1 dram0 permission monitor interrupt."]
49    #[inline(always)]
50    pub fn core_1_dram0_pms_monitor_violate_en(
51        &mut self,
52    ) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
53        CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
54    }
55}
56#[doc = "core1 dram0 permission monitor configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_dram0_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct CORE_1_DRAM0_PMS_MONITOR_1_SPEC;
58impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`core_1_dram0_pms_monitor_1::R`](R) reader structure"]
62impl crate::Readable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {}
63#[doc = "`write(|w| ..)` method takes [`core_1_dram0_pms_monitor_1::W`](W) writer structure"]
64impl crate::Writable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
65    type Safety = crate::Unsafe;
66    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
67    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68}
69#[doc = "`reset()` method sets CORE_1_DRAM0_PMS_MONITOR_1 to value 0x03"]
70impl crate::Resettable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
71    const RESET_VALUE: u32 = 0x03;
72}
esp32s3/sensitive/core_1_dram0_pms_monitor_1.rs

esp32s3/sensitive/
core_1_dram0_pms_monitor_1.rs
