Module cache_fctrl

Source
Expand description

SPI1 bit mode control register.

Structs§

CACHE_FCTRL_SPEC
SPI1 bit mode control register.

Type Aliases§

CACHE_USR_CMD_4BYTE_R
Field CACHE_USR_CMD_4BYTE reader - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
CACHE_USR_CMD_4BYTE_W
Field CACHE_USR_CMD_4BYTE writer - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
FADDR_DUAL_R
Field FADDR_DUAL reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.
FADDR_DUAL_W
Field FADDR_DUAL writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.
FADDR_QUAD_R
Field FADDR_QUAD reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.
FADDR_QUAD_W
Field FADDR_QUAD writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.
FDIN_DUAL_R
Field FDIN_DUAL reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.
FDIN_DUAL_W
Field FDIN_DUAL writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.
FDIN_QUAD_R
Field FDIN_QUAD reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.
FDIN_QUAD_W
Field FDIN_QUAD writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.
FDOUT_DUAL_R
Field FDOUT_DUAL reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.
FDOUT_DUAL_W
Field FDOUT_DUAL writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.
FDOUT_QUAD_R
Field FDOUT_QUAD reader - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.
FDOUT_QUAD_W
Field FDOUT_QUAD writer - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.
R
Register CACHE_FCTRL reader
W
Register CACHE_FCTRL writer