Type Alias R

Source
pub type R = R<CTRL_SPEC>;
Expand description

Register CTRL reader

Aliased Type§

struct R { /* private fields */ }

Implementations§

Source§

impl R

Source

pub fn fdummy_out(&self) -> FDUMMY_OUT_R

Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

Source

pub fn fdout_oct(&self) -> FDOUT_OCT_R

Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.

Source

pub fn fdin_oct(&self) -> FDIN_OCT_R

Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase.

Source

pub fn faddr_oct(&self) -> FADDR_OCT_R

Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.

Source

pub fn fcmd_dual(&self) -> FCMD_DUAL_R

Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase.

Source

pub fn fcmd_quad(&self) -> FCMD_QUAD_R

Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase.

Source

pub fn fcmd_oct(&self) -> FCMD_OCT_R

Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase.

Source

pub fn fastrd_mode(&self) -> FASTRD_MODE_R

Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.

Source

pub fn fread_dual(&self) -> FREAD_DUAL_R

Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.

Source

pub fn q_pol(&self) -> Q_POL_R

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

Source

pub fn d_pol(&self) -> D_POL_R

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

Source

pub fn fread_quad(&self) -> FREAD_QUAD_R

Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.

Source

pub fn wp(&self) -> WP_R

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

Source

pub fn fread_dio(&self) -> FREAD_DIO_R

Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.

Source

pub fn fread_qio(&self) -> FREAD_QIO_R

Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.