Type Alias R

pub type R = R<INT_ST_SPEC>;

Register INT_ST reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R

This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.

pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_

Iterator for array of: This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

pub fn timer0_ovf(&self) -> TIMER_OVF_R

Bit 0 - This is the masked interrupt status bit for the TIMER0_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

pub fn timer1_ovf(&self) -> TIMER_OVF_R

Bit 1 - This is the masked interrupt status bit for the TIMER1_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

pub fn timer2_ovf(&self) -> TIMER_OVF_R

Bit 2 - This is the masked interrupt status bit for the TIMER2_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

pub fn timer3_ovf(&self) -> TIMER_OVF_R

Bit 3 - This is the masked interrupt status bit for the TIMER3_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1.

pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R

This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-7) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.

pub fn duty_chng_end_ch_iter( &self, ) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_

Iterator for array of: This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-7) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R

Bit 4 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH0 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R

Bit 5 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH1 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R

Bit 6 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH2 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R

Bit 7 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH3 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R

Bit 8 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH4 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R

Bit 9 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH5 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch6(&self) -> DUTY_CHNG_END_CH_R

Bit 10 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH6 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn duty_chng_end_ch7(&self) -> DUTY_CHNG_END_CH_R

Bit 11 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH7 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1.

pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R

This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-7) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.

pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_

Iterator for array of: This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-7) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R

Bit 12 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH0 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R

Bit 13 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH1 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R

Bit 14 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH2 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R

Bit 15 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH3 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R

Bit 16 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH4 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R

Bit 17 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH5 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch6(&self) -> OVF_CNT_CH_R

Bit 18 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH6 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.

pub fn ovf_cnt_ch7(&self) -> OVF_CNT_CH_R

Bit 19 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH7 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1.