Type Alias W

pub type W = W<LCD_CLOCK_SPEC>;

Register LCD_CLOCK writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn lcd_clkcnt_n(&mut self) -> LCD_CLKCNT_N_W<'_, LCD_CLOCK_SPEC>

Bits 0:5 - f_{LCD_PCLK} = f_{LCD_CLK}/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0.

pub fn lcd_clk_equ_sysclk(&mut self) -> LCD_CLK_EQU_SYSCLK_W<'_, LCD_CLOCK_SPEC>

Bit 6 - 1: f_{LCD_PCLK} = f_{LCD_CLK}. 0: f_{LCD_PCLK} = f_{LCD_CLK}/(LCD_CAM_LCD_CLKCNT_N + 1).

pub fn lcd_ck_idle_edge(&mut self) -> LCD_CK_IDLE_EDGE_W<'_, LCD_CLOCK_SPEC>

Bit 7 - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle.

pub fn lcd_ck_out_edge(&mut self) -> LCD_CK_OUT_EDGE_W<'_, LCD_CLOCK_SPEC>

Bit 8 - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle.

pub fn lcd_clkm_div_num(&mut self) -> LCD_CLKM_DIV_NUM_W<'_, LCD_CLOCK_SPEC>

Bits 9:16 - Integral LCD clock divider value.

pub fn lcd_clkm_div_b(&mut self) -> LCD_CLKM_DIV_B_W<'_, LCD_CLOCK_SPEC>

Bits 17:22 - Fractional clock divider numerator value.

pub fn lcd_clkm_div_a(&mut self) -> LCD_CLKM_DIV_A_W<'_, LCD_CLOCK_SPEC>

Bits 23:28 - Fractional clock divider denominator value.

pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W<'_, LCD_CLOCK_SPEC>

Bits 29:30 - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.

pub fn clk_en(&mut self) -> CLK_EN_W<'_, LCD_CLOCK_SPEC>

Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used.