Type Alias W

pub type W = W<CAM_CTRL_SPEC>;

Register CAM_CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn cam_stop_en(&mut self) -> CAM_STOP_EN_W<'_, CAM_CTRL_SPEC>

Bit 0 - Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop.

pub fn cam_vsync_filter_thres( &mut self, ) -> CAM_VSYNC_FILTER_THRES_W<'_, CAM_CTRL_SPEC>

Bits 1:3 - Filter threshold value for CAM_VSYNC signal.

pub fn cam_update(&mut self) -> CAM_UPDATE_W<'_, CAM_CTRL_SPEC>

Bit 4 - 1: Update camera registers. This bit is cleared by hardware. 0: Do not care.

pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W<'_, CAM_CTRL_SPEC>

Bit 5 - 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change.

pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W<'_, CAM_CTRL_SPEC>

Bit 6 - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change.

pub fn cam_line_int_en(&mut self) -> CAM_LINE_INT_EN_W<'_, CAM_CTRL_SPEC>

Bit 7 - 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable.

pub fn cam_vs_eof_en(&mut self) -> CAM_VS_EOF_EN_W<'_, CAM_CTRL_SPEC>

Bit 8 - 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN.

pub fn cam_clkm_div_num(&mut self) -> CAM_CLKM_DIV_NUM_W<'_, CAM_CTRL_SPEC>

Bits 9:16 - Integral camera clock divider value.

pub fn cam_clkm_div_b(&mut self) -> CAM_CLKM_DIV_B_W<'_, CAM_CTRL_SPEC>

Bits 17:22 - Fractional clock divider numerator value.

pub fn cam_clkm_div_a(&mut self) -> CAM_CLKM_DIV_A_W<'_, CAM_CTRL_SPEC>

Bits 23:28 - Fractional clock divider denominator value.

pub fn cam_clk_sel(&mut self) -> CAM_CLK_SEL_W<'_, CAM_CTRL_SPEC>

Bits 29:30 - Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK.