Struct CH

#[repr(C)]
pub struct CH { /* private fields */ }

Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?

Implementations

impl CH

pub const fn in_conf0(&self) -> &IN_CONF0

0x00 - Configure 0 register of Rx channel 0

pub const fn in_conf1(&self) -> &IN_CONF1

0x04 - Configure 1 register of Rx channel 0

pub const fn in_int(&self) -> &IN_INT

0x08..0x18 - Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR

pub const fn infifo_status(&self) -> &INFIFO_STATUS

0x18 - Receive FIFO status of Rx channel 0

pub const fn in_pop(&self) -> &IN_POP

0x1c - Pop control register of Rx channel 0

pub const fn in_link(&self) -> &IN_LINK

0x20 - Link descriptor configure and control register of Rx channel 0

pub const fn in_state(&self) -> &IN_STATE

0x24 - Receive status of Rx channel 0

pub const fn in_suc_eof_des_addr(&self) -> &IN_SUC_EOF_DES_ADDR

0x28 - Inlink descriptor address when EOF occurs of Rx channel 0

pub const fn in_err_eof_des_addr(&self) -> &IN_ERR_EOF_DES_ADDR

0x2c - Inlink descriptor address when errors occur of Rx channel 0

pub const fn in_dscr(&self) -> &IN_DSCR

0x30 - Current inlink descriptor address of Rx channel 0

pub const fn in_dscr_bf0(&self) -> &IN_DSCR_BF0

0x34 - The last inlink descriptor address of Rx channel 0

pub const fn in_dscr_bf1(&self) -> &IN_DSCR_BF1

0x38 - The second-to-last inlink descriptor address of Rx channel 0

pub const fn in_wight(&self) -> &IN_WIGHT

0x3c - Weight register of Rx channel 0

pub const fn in_pri(&self) -> &IN_PRI

0x44 - Priority register of Rx channel 0

pub const fn in_peri_sel(&self) -> &IN_PERI_SEL

0x48 - Peripheral selection of Rx channel 0

pub const fn out_conf0(&self) -> &OUT_CONF0

0x60 - Configure 0 register of Tx channel 0

pub const fn out_conf1(&self) -> &OUT_CONF1

0x64 - Configure 1 register of Tx channel 0

pub const fn out_int(&self) -> &OUT_INT

0x68..0x78 - Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR

pub const fn outfifo_status(&self) -> &OUTFIFO_STATUS

0x78 - Transmit FIFO status of Tx channel 0

pub const fn out_push(&self) -> &OUT_PUSH

0x7c - Push control register of Rx channel 0

pub const fn out_link(&self) -> &OUT_LINK

0x80 - Link descriptor configure and control register of Tx channel 0

pub const fn out_state(&self) -> &OUT_STATE

0x84 - Transmit status of Tx channel 0

pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR

0x88 - Outlink descriptor address when EOF occurs of Tx channel 0

pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR

0x8c - The last outlink descriptor address when EOF occurs of Tx channel 0

pub const fn out_dscr(&self) -> &OUT_DSCR

0x90 - Current inlink descriptor address of Tx channel 0

pub const fn out_dscr_bf0(&self) -> &OUT_DSCR_BF0

0x94 - The last inlink descriptor address of Tx channel 0

pub const fn out_dscr_bf1(&self) -> &OUT_DSCR_BF1

0x98 - The second-to-last inlink descriptor address of Tx channel 0

pub const fn out_wight(&self) -> &OUT_WIGHT

0x9c - Weight register of Rx channel 0

pub const fn out_pri(&self) -> &OUT_PRI

0xa4 - Priority register of Tx channel 0.

pub const fn out_peri_sel(&self) -> &OUT_PERI_SEL

0xa8 - Peripheral selection of Tx channel 0