esp32s3/lcd_cam/
lcd_clock.rs

1#[doc = "Register `LCD_CLOCK` reader"]
2pub type R = crate::R<LCD_CLOCK_SPEC>;
3#[doc = "Register `LCD_CLOCK` writer"]
4pub type W = crate::W<LCD_CLOCK_SPEC>;
5#[doc = "Field `LCD_CLKCNT_N` reader - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
6pub type LCD_CLKCNT_N_R = crate::FieldReader;
7#[doc = "Field `LCD_CLKCNT_N` writer - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
8pub type LCD_CLKCNT_N_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `LCD_CLK_EQU_SYSCLK` reader - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
10pub type LCD_CLK_EQU_SYSCLK_R = crate::BitReader;
11#[doc = "Field `LCD_CLK_EQU_SYSCLK` writer - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
12pub type LCD_CLK_EQU_SYSCLK_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LCD_CK_IDLE_EDGE` reader - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
14pub type LCD_CK_IDLE_EDGE_R = crate::BitReader;
15#[doc = "Field `LCD_CK_IDLE_EDGE` writer - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
16pub type LCD_CK_IDLE_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LCD_CK_OUT_EDGE` reader - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle."]
18pub type LCD_CK_OUT_EDGE_R = crate::BitReader;
19#[doc = "Field `LCD_CK_OUT_EDGE` writer - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle."]
20pub type LCD_CK_OUT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `LCD_CLKM_DIV_NUM` reader - Integral LCD clock divider value."]
22pub type LCD_CLKM_DIV_NUM_R = crate::FieldReader;
23#[doc = "Field `LCD_CLKM_DIV_NUM` writer - Integral LCD clock divider value."]
24pub type LCD_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `LCD_CLKM_DIV_B` reader - Fractional clock divider numerator value."]
26pub type LCD_CLKM_DIV_B_R = crate::FieldReader;
27#[doc = "Field `LCD_CLKM_DIV_B` writer - Fractional clock divider numerator value."]
28pub type LCD_CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
29#[doc = "Field `LCD_CLKM_DIV_A` reader - Fractional clock divider denominator value."]
30pub type LCD_CLKM_DIV_A_R = crate::FieldReader;
31#[doc = "Field `LCD_CLKM_DIV_A` writer - Fractional clock divider denominator value."]
32pub type LCD_CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
33#[doc = "Field `LCD_CLK_SEL` reader - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
34pub type LCD_CLK_SEL_R = crate::FieldReader;
35#[doc = "Field `LCD_CLK_SEL` writer - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
36pub type LCD_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
37#[doc = "Field `CLK_EN` reader - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
38pub type CLK_EN_R = crate::BitReader;
39#[doc = "Field `CLK_EN` writer - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
40pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bits 0:5 - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
43    #[inline(always)]
44    pub fn lcd_clkcnt_n(&self) -> LCD_CLKCNT_N_R {
45        LCD_CLKCNT_N_R::new((self.bits & 0x3f) as u8)
46    }
47    #[doc = "Bit 6 - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
48    #[inline(always)]
49    pub fn lcd_clk_equ_sysclk(&self) -> LCD_CLK_EQU_SYSCLK_R {
50        LCD_CLK_EQU_SYSCLK_R::new(((self.bits >> 6) & 1) != 0)
51    }
52    #[doc = "Bit 7 - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
53    #[inline(always)]
54    pub fn lcd_ck_idle_edge(&self) -> LCD_CK_IDLE_EDGE_R {
55        LCD_CK_IDLE_EDGE_R::new(((self.bits >> 7) & 1) != 0)
56    }
57    #[doc = "Bit 8 - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle."]
58    #[inline(always)]
59    pub fn lcd_ck_out_edge(&self) -> LCD_CK_OUT_EDGE_R {
60        LCD_CK_OUT_EDGE_R::new(((self.bits >> 8) & 1) != 0)
61    }
62    #[doc = "Bits 9:16 - Integral LCD clock divider value."]
63    #[inline(always)]
64    pub fn lcd_clkm_div_num(&self) -> LCD_CLKM_DIV_NUM_R {
65        LCD_CLKM_DIV_NUM_R::new(((self.bits >> 9) & 0xff) as u8)
66    }
67    #[doc = "Bits 17:22 - Fractional clock divider numerator value."]
68    #[inline(always)]
69    pub fn lcd_clkm_div_b(&self) -> LCD_CLKM_DIV_B_R {
70        LCD_CLKM_DIV_B_R::new(((self.bits >> 17) & 0x3f) as u8)
71    }
72    #[doc = "Bits 23:28 - Fractional clock divider denominator value."]
73    #[inline(always)]
74    pub fn lcd_clkm_div_a(&self) -> LCD_CLKM_DIV_A_R {
75        LCD_CLKM_DIV_A_R::new(((self.bits >> 23) & 0x3f) as u8)
76    }
77    #[doc = "Bits 29:30 - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
78    #[inline(always)]
79    pub fn lcd_clk_sel(&self) -> LCD_CLK_SEL_R {
80        LCD_CLK_SEL_R::new(((self.bits >> 29) & 3) as u8)
81    }
82    #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
83    #[inline(always)]
84    pub fn clk_en(&self) -> CLK_EN_R {
85        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("LCD_CLOCK")
92            .field("lcd_clkcnt_n", &self.lcd_clkcnt_n())
93            .field("lcd_clk_equ_sysclk", &self.lcd_clk_equ_sysclk())
94            .field("lcd_ck_idle_edge", &self.lcd_ck_idle_edge())
95            .field("lcd_ck_out_edge", &self.lcd_ck_out_edge())
96            .field("lcd_clkm_div_num", &self.lcd_clkm_div_num())
97            .field("lcd_clkm_div_b", &self.lcd_clkm_div_b())
98            .field("lcd_clkm_div_a", &self.lcd_clkm_div_a())
99            .field("lcd_clk_sel", &self.lcd_clk_sel())
100            .field("clk_en", &self.clk_en())
101            .finish()
102    }
103}
104impl W {
105    #[doc = "Bits 0:5 - f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
106    #[inline(always)]
107    pub fn lcd_clkcnt_n(&mut self) -> LCD_CLKCNT_N_W<LCD_CLOCK_SPEC> {
108        LCD_CLKCNT_N_W::new(self, 0)
109    }
110    #[doc = "Bit 6 - 1: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB> = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1)."]
111    #[inline(always)]
112    pub fn lcd_clk_equ_sysclk(&mut self) -> LCD_CLK_EQU_SYSCLK_W<LCD_CLOCK_SPEC> {
113        LCD_CLK_EQU_SYSCLK_W::new(self, 6)
114    }
115    #[doc = "Bit 7 - 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle."]
116    #[inline(always)]
117    pub fn lcd_ck_idle_edge(&mut self) -> LCD_CK_IDLE_EDGE_W<LCD_CLOCK_SPEC> {
118        LCD_CK_IDLE_EDGE_W::new(self, 7)
119    }
120    #[doc = "Bit 8 - 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle."]
121    #[inline(always)]
122    pub fn lcd_ck_out_edge(&mut self) -> LCD_CK_OUT_EDGE_W<LCD_CLOCK_SPEC> {
123        LCD_CK_OUT_EDGE_W::new(self, 8)
124    }
125    #[doc = "Bits 9:16 - Integral LCD clock divider value."]
126    #[inline(always)]
127    pub fn lcd_clkm_div_num(&mut self) -> LCD_CLKM_DIV_NUM_W<LCD_CLOCK_SPEC> {
128        LCD_CLKM_DIV_NUM_W::new(self, 9)
129    }
130    #[doc = "Bits 17:22 - Fractional clock divider numerator value."]
131    #[inline(always)]
132    pub fn lcd_clkm_div_b(&mut self) -> LCD_CLKM_DIV_B_W<LCD_CLOCK_SPEC> {
133        LCD_CLKM_DIV_B_W::new(self, 17)
134    }
135    #[doc = "Bits 23:28 - Fractional clock divider denominator value."]
136    #[inline(always)]
137    pub fn lcd_clkm_div_a(&mut self) -> LCD_CLKM_DIV_A_W<LCD_CLOCK_SPEC> {
138        LCD_CLKM_DIV_A_W::new(self, 23)
139    }
140    #[doc = "Bits 29:30 - Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK."]
141    #[inline(always)]
142    pub fn lcd_clk_sel(&mut self) -> LCD_CLK_SEL_W<LCD_CLOCK_SPEC> {
143        LCD_CLK_SEL_W::new(self, 29)
144    }
145    #[doc = "Bit 31 - Set this bit to force enable the clock for all configuration registers. Clock gate is not used."]
146    #[inline(always)]
147    pub fn clk_en(&mut self) -> CLK_EN_W<LCD_CLOCK_SPEC> {
148        CLK_EN_W::new(self, 31)
149    }
150}
151#[doc = "LCD clock configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`lcd_clock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lcd_clock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct LCD_CLOCK_SPEC;
153impl crate::RegisterSpec for LCD_CLOCK_SPEC {
154    type Ux = u32;
155}
156#[doc = "`read()` method returns [`lcd_clock::R`](R) reader structure"]
157impl crate::Readable for LCD_CLOCK_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`lcd_clock::W`](W) writer structure"]
159impl crate::Writable for LCD_CLOCK_SPEC {
160    type Safety = crate::Unsafe;
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets LCD_CLOCK to value 0"]
165impl crate::Resettable for LCD_CLOCK_SPEC {
166    const RESET_VALUE: u32 = 0;
167}
esp32s3/lcd_cam/lcd_clock.rs

esp32s3/lcd_cam/
lcd_clock.rs
