esp32s3/dma/ch/
out_conf0.rs

1#[doc = "Register `OUT_CONF0` reader"]
2pub type R = crate::R<OUT_CONF0_SPEC>;
3#[doc = "Register `OUT_CONF0` writer"]
4pub type W = crate::W<OUT_CONF0_SPEC>;
5#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
6pub type OUT_RST_R = crate::BitReader;
7#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
8pub type OUT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `OUT_LOOP_TEST` reader - reserved"]
10pub type OUT_LOOP_TEST_R = crate::BitReader;
11#[doc = "Field `OUT_LOOP_TEST` writer - reserved"]
12pub type OUT_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
14pub type OUT_AUTO_WRBACK_R = crate::BitReader;
15#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
16pub type OUT_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
18pub type OUT_EOF_MODE_R = crate::BitReader;
19#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
20pub type OUT_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
22pub type OUTDSCR_BURST_EN_R = crate::BitReader;
23#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
24pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
26pub type OUT_DATA_BURST_EN_R = crate::BitReader;
27#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
28pub type OUT_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
31    #[inline(always)]
32    pub fn out_rst(&self) -> OUT_RST_R {
33        OUT_RST_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - reserved"]
36    #[inline(always)]
37    pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R {
38        OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
41    #[inline(always)]
42    pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R {
43        OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
46    #[inline(always)]
47    pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R {
48        OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
51    #[inline(always)]
52    pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R {
53        OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
56    #[inline(always)]
57    pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R {
58        OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("OUT_CONF0")
65            .field("out_rst", &self.out_rst())
66            .field("out_loop_test", &self.out_loop_test())
67            .field("out_auto_wrback", &self.out_auto_wrback())
68            .field("out_eof_mode", &self.out_eof_mode())
69            .field("outdscr_burst_en", &self.outdscr_burst_en())
70            .field("out_data_burst_en", &self.out_data_burst_en())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
76    #[inline(always)]
77    pub fn out_rst(&mut self) -> OUT_RST_W<OUT_CONF0_SPEC> {
78        OUT_RST_W::new(self, 0)
79    }
80    #[doc = "Bit 1 - reserved"]
81    #[inline(always)]
82    pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<OUT_CONF0_SPEC> {
83        OUT_LOOP_TEST_W::new(self, 1)
84    }
85    #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
86    #[inline(always)]
87    pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<OUT_CONF0_SPEC> {
88        OUT_AUTO_WRBACK_W::new(self, 2)
89    }
90    #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
91    #[inline(always)]
92    pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<OUT_CONF0_SPEC> {
93        OUT_EOF_MODE_W::new(self, 3)
94    }
95    #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
96    #[inline(always)]
97    pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<OUT_CONF0_SPEC> {
98        OUTDSCR_BURST_EN_W::new(self, 4)
99    }
100    #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
101    #[inline(always)]
102    pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<OUT_CONF0_SPEC> {
103        OUT_DATA_BURST_EN_W::new(self, 5)
104    }
105}
106#[doc = "Configure 0 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct OUT_CONF0_SPEC;
108impl crate::RegisterSpec for OUT_CONF0_SPEC {
109    type Ux = u32;
110}
111#[doc = "`read()` method returns [`out_conf0::R`](R) reader structure"]
112impl crate::Readable for OUT_CONF0_SPEC {}
113#[doc = "`write(|w| ..)` method takes [`out_conf0::W`](W) writer structure"]
114impl crate::Writable for OUT_CONF0_SPEC {
115    type Safety = crate::Unsafe;
116    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
117    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
118}
119#[doc = "`reset()` method sets OUT_CONF0 to value 0x08"]
120impl crate::Resettable for OUT_CONF0_SPEC {
121    const RESET_VALUE: u32 = 0x08;
122}
esp32s3/dma/ch/out_conf0.rs

esp32s3/dma/ch/
out_conf0.rs
