Struct SRAM_CLK_SPEC

pub struct SRAM_CLK_SPEC;

SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

You can read this register and get sram_clk::R. You can reset, write, write_with_zero this register using sram_clk::W. You can also modify this register. See API.

Trait Implementations

impl RegisterSpec for SRAM_CLK_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SRAM_CLK_SPEC

reset() method sets SRAM_CLK to value 0x0003_0103

const RESET_VALUE: u32 = 196_867u32

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for SRAM_CLK_SPEC

write(|w| ..) method takes sram_clk::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0u32

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1

type Safety = Unsafe

Is it safe to write any bits to register

impl Readable for SRAM_CLK_SPEC

read() method returns sram_clk::R reader structure