esp32s3/extmem/
icache_ctrl.rs

1#[doc = "Register `ICACHE_CTRL` reader"]
2pub type R = crate::R<ICACHE_CTRL_SPEC>;
3#[doc = "Register `ICACHE_CTRL` writer"]
4pub type W = crate::W<ICACHE_CTRL_SPEC>;
5#[doc = "Field `ICACHE_ENABLE` reader - The bit is used to activate the data cache. 0: disable, 1: enable"]
6pub type ICACHE_ENABLE_R = crate::BitReader;
7#[doc = "Field `ICACHE_ENABLE` writer - The bit is used to activate the data cache. 0: disable, 1: enable"]
8pub type ICACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ICACHE_WAY_MODE` reader - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
10pub type ICACHE_WAY_MODE_R = crate::BitReader;
11#[doc = "Field `ICACHE_WAY_MODE` writer - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
12pub type ICACHE_WAY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ICACHE_SIZE_MODE` reader - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
14pub type ICACHE_SIZE_MODE_R = crate::BitReader;
15#[doc = "Field `ICACHE_SIZE_MODE` writer - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
16pub type ICACHE_SIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ICACHE_BLOCKSIZE_MODE` reader - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
18pub type ICACHE_BLOCKSIZE_MODE_R = crate::BitReader;
19#[doc = "Field `ICACHE_BLOCKSIZE_MODE` writer - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
20pub type ICACHE_BLOCKSIZE_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
23    #[inline(always)]
24    pub fn icache_enable(&self) -> ICACHE_ENABLE_R {
25        ICACHE_ENABLE_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
28    #[inline(always)]
29    pub fn icache_way_mode(&self) -> ICACHE_WAY_MODE_R {
30        ICACHE_WAY_MODE_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
33    #[inline(always)]
34    pub fn icache_size_mode(&self) -> ICACHE_SIZE_MODE_R {
35        ICACHE_SIZE_MODE_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
38    #[inline(always)]
39    pub fn icache_blocksize_mode(&self) -> ICACHE_BLOCKSIZE_MODE_R {
40        ICACHE_BLOCKSIZE_MODE_R::new(((self.bits >> 3) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("ICACHE_CTRL")
47            .field("icache_enable", &self.icache_enable())
48            .field("icache_way_mode", &self.icache_way_mode())
49            .field("icache_size_mode", &self.icache_size_mode())
50            .field("icache_blocksize_mode", &self.icache_blocksize_mode())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
56    #[inline(always)]
57    pub fn icache_enable(&mut self) -> ICACHE_ENABLE_W<ICACHE_CTRL_SPEC> {
58        ICACHE_ENABLE_W::new(self, 0)
59    }
60    #[doc = "Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way"]
61    #[inline(always)]
62    pub fn icache_way_mode(&mut self) -> ICACHE_WAY_MODE_W<ICACHE_CTRL_SPEC> {
63        ICACHE_WAY_MODE_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB"]
66    #[inline(always)]
67    pub fn icache_size_mode(&mut self) -> ICACHE_SIZE_MODE_W<ICACHE_CTRL_SPEC> {
68        ICACHE_SIZE_MODE_W::new(self, 2)
69    }
70    #[doc = "Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes"]
71    #[inline(always)]
72    pub fn icache_blocksize_mode(&mut self) -> ICACHE_BLOCKSIZE_MODE_W<ICACHE_CTRL_SPEC> {
73        ICACHE_BLOCKSIZE_MODE_W::new(self, 3)
74    }
75}
76#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct ICACHE_CTRL_SPEC;
78impl crate::RegisterSpec for ICACHE_CTRL_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`icache_ctrl::R`](R) reader structure"]
82impl crate::Readable for ICACHE_CTRL_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`icache_ctrl::W`](W) writer structure"]
84impl crate::Writable for ICACHE_CTRL_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets ICACHE_CTRL to value 0"]
90impl crate::Resettable for ICACHE_CTRL_SPEC {
91    const RESET_VALUE: u32 = 0;
92}
esp32s3/extmem/icache_ctrl.rs

esp32s3/extmem/
icache_ctrl.rs
