esp32s3/rmt/
ch_rx_conf0.rs

1#[doc = "Register `CH%s_RX_CONF0` reader"]
2pub type R = crate::R<CH_RX_CONF0_SPEC>;
3#[doc = "Register `CH%s_RX_CONF0` writer"]
4pub type W = crate::W<CH_RX_CONF0_SPEC>;
5#[doc = "Field `DIV_CNT` reader - This register is used to configure the divider for clock of CHANNEL%s."]
6pub type DIV_CNT_R = crate::FieldReader;
7#[doc = "Field `DIV_CNT` writer - This register is used to configure the divider for clock of CHANNEL%s."]
8pub type DIV_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `IDLE_THRES` reader - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
10pub type IDLE_THRES_R = crate::FieldReader<u16>;
11#[doc = "Field `IDLE_THRES` writer - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
12pub type IDLE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
13#[doc = "Field `MEM_SIZE` reader - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
14pub type MEM_SIZE_R = crate::FieldReader;
15#[doc = "Field `MEM_SIZE` writer - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
16pub type MEM_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CARRIER_EN` reader - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
18pub type CARRIER_EN_R = crate::BitReader;
19#[doc = "Field `CARRIER_EN` writer - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
20pub type CARRIER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CARRIER_OUT_LV` reader - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
22pub type CARRIER_OUT_LV_R = crate::BitReader;
23#[doc = "Field `CARRIER_OUT_LV` writer - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
24pub type CARRIER_OUT_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
27    #[inline(always)]
28    pub fn div_cnt(&self) -> DIV_CNT_R {
29        DIV_CNT_R::new((self.bits & 0xff) as u8)
30    }
31    #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
32    #[inline(always)]
33    pub fn idle_thres(&self) -> IDLE_THRES_R {
34        IDLE_THRES_R::new(((self.bits >> 8) & 0x7fff) as u16)
35    }
36    #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
37    #[inline(always)]
38    pub fn mem_size(&self) -> MEM_SIZE_R {
39        MEM_SIZE_R::new(((self.bits >> 24) & 0x0f) as u8)
40    }
41    #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
42    #[inline(always)]
43    pub fn carrier_en(&self) -> CARRIER_EN_R {
44        CARRIER_EN_R::new(((self.bits >> 28) & 1) != 0)
45    }
46    #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
47    #[inline(always)]
48    pub fn carrier_out_lv(&self) -> CARRIER_OUT_LV_R {
49        CARRIER_OUT_LV_R::new(((self.bits >> 29) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("CH_RX_CONF0")
56            .field("div_cnt", &self.div_cnt())
57            .field("idle_thres", &self.idle_thres())
58            .field("mem_size", &self.mem_size())
59            .field("carrier_en", &self.carrier_en())
60            .field("carrier_out_lv", &self.carrier_out_lv())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
66    #[inline(always)]
67    pub fn div_cnt(&mut self) -> DIV_CNT_W<CH_RX_CONF0_SPEC> {
68        DIV_CNT_W::new(self, 0)
69    }
70    #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
71    #[inline(always)]
72    pub fn idle_thres(&mut self) -> IDLE_THRES_W<CH_RX_CONF0_SPEC> {
73        IDLE_THRES_W::new(self, 8)
74    }
75    #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
76    #[inline(always)]
77    pub fn mem_size(&mut self) -> MEM_SIZE_W<CH_RX_CONF0_SPEC> {
78        MEM_SIZE_W::new(self, 24)
79    }
80    #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
81    #[inline(always)]
82    pub fn carrier_en(&mut self) -> CARRIER_EN_W<CH_RX_CONF0_SPEC> {
83        CARRIER_EN_W::new(self, 28)
84    }
85    #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level."]
86    #[inline(always)]
87    pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<CH_RX_CONF0_SPEC> {
88        CARRIER_OUT_LV_W::new(self, 29)
89    }
90}
91#[doc = "Channel %s configure register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_rx_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_rx_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CH_RX_CONF0_SPEC;
93impl crate::RegisterSpec for CH_RX_CONF0_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`ch_rx_conf0::R`](R) reader structure"]
97impl crate::Readable for CH_RX_CONF0_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`ch_rx_conf0::W`](W) writer structure"]
99impl crate::Writable for CH_RX_CONF0_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets CH%s_RX_CONF0 to value 0x317f_ff02"]
105impl crate::Resettable for CH_RX_CONF0_SPEC {
106    const RESET_VALUE: u32 = 0x317f_ff02;
107}
esp32s3/rmt/ch_rx_conf0.rs

esp32s3/rmt/
ch_rx_conf0.rs
