esp32s3/apb_saradc/
fsm_wait.rs

1#[doc = "Register `FSM_WAIT` reader"]
2pub type R = crate::R<FSM_WAIT_SPEC>;
3#[doc = "Register `FSM_WAIT` writer"]
4pub type W = crate::W<FSM_WAIT_SPEC>;
5#[doc = "Field `XPD_WAIT` reader - the cycle which saradc controller in xpd state"]
6pub type XPD_WAIT_R = crate::FieldReader;
7#[doc = "Field `XPD_WAIT` writer - the cycle which saradc controller in xpd state"]
8pub type XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `RSTB_WAIT` reader - the cycle which saradc controller in rst state"]
10pub type RSTB_WAIT_R = crate::FieldReader;
11#[doc = "Field `RSTB_WAIT` writer - the cycle which saradc controller in rst state"]
12pub type RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `STANDBY_WAIT` reader - the cycle which saradc controller in standby state"]
14pub type STANDBY_WAIT_R = crate::FieldReader;
15#[doc = "Field `STANDBY_WAIT` writer - the cycle which saradc controller in standby state"]
16pub type STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17impl R {
18    #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
19    #[inline(always)]
20    pub fn xpd_wait(&self) -> XPD_WAIT_R {
21        XPD_WAIT_R::new((self.bits & 0xff) as u8)
22    }
23    #[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
24    #[inline(always)]
25    pub fn rstb_wait(&self) -> RSTB_WAIT_R {
26        RSTB_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
27    }
28    #[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
29    #[inline(always)]
30    pub fn standby_wait(&self) -> STANDBY_WAIT_R {
31        STANDBY_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("FSM_WAIT")
38            .field("xpd_wait", &self.xpd_wait())
39            .field("rstb_wait", &self.rstb_wait())
40            .field("standby_wait", &self.standby_wait())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
46    #[inline(always)]
47    pub fn xpd_wait(&mut self) -> XPD_WAIT_W<FSM_WAIT_SPEC> {
48        XPD_WAIT_W::new(self, 0)
49    }
50    #[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
51    #[inline(always)]
52    pub fn rstb_wait(&mut self) -> RSTB_WAIT_W<FSM_WAIT_SPEC> {
53        RSTB_WAIT_W::new(self, 8)
54    }
55    #[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
56    #[inline(always)]
57    pub fn standby_wait(&mut self) -> STANDBY_WAIT_W<FSM_WAIT_SPEC> {
58        STANDBY_WAIT_W::new(self, 16)
59    }
60}
61#[doc = "configure apb saradc fsm\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_wait::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsm_wait::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct FSM_WAIT_SPEC;
63impl crate::RegisterSpec for FSM_WAIT_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`fsm_wait::R`](R) reader structure"]
67impl crate::Readable for FSM_WAIT_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`fsm_wait::W`](W) writer structure"]
69impl crate::Writable for FSM_WAIT_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets FSM_WAIT to value 0x00ff_0808"]
75impl crate::Resettable for FSM_WAIT_SPEC {
76    const RESET_VALUE: u32 = 0x00ff_0808;
77}
esp32s3/apb_saradc/fsm_wait.rs

esp32s3/apb_saradc/
fsm_wait.rs
