esp32s3/extmem/
icache_atomic_operate_ena.rs

1#[doc = "Register `ICACHE_ATOMIC_OPERATE_ENA` reader"]
2pub type R = crate::R<ICACHE_ATOMIC_OPERATE_ENA_SPEC>;
3#[doc = "Register `ICACHE_ATOMIC_OPERATE_ENA` writer"]
4pub type W = crate::W<ICACHE_ATOMIC_OPERATE_ENA_SPEC>;
5#[doc = "Field `ICACHE_ATOMIC_OPERATE_ENA` reader - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
6pub type ICACHE_ATOMIC_OPERATE_ENA_R = crate::BitReader;
7#[doc = "Field `ICACHE_ATOMIC_OPERATE_ENA` writer - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
8pub type ICACHE_ATOMIC_OPERATE_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
11    #[inline(always)]
12    pub fn icache_atomic_operate_ena(&self) -> ICACHE_ATOMIC_OPERATE_ENA_R {
13        ICACHE_ATOMIC_OPERATE_ENA_R::new((self.bits & 1) != 0)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("ICACHE_ATOMIC_OPERATE_ENA")
20            .field(
21                "icache_atomic_operate_ena",
22                &self.icache_atomic_operate_ena(),
23            )
24            .finish()
25    }
26}
27impl W {
28    #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
29    #[inline(always)]
30    pub fn icache_atomic_operate_ena(
31        &mut self,
32    ) -> ICACHE_ATOMIC_OPERATE_ENA_W<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
33        ICACHE_ATOMIC_OPERATE_ENA_W::new(self, 0)
34    }
35}
36#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`icache_atomic_operate_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icache_atomic_operate_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct ICACHE_ATOMIC_OPERATE_ENA_SPEC;
38impl crate::RegisterSpec for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`icache_atomic_operate_ena::R`](R) reader structure"]
42impl crate::Readable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {}
43#[doc = "`write(|w| ..)` method takes [`icache_atomic_operate_ena::W`](W) writer structure"]
44impl crate::Writable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
45    type Safety = crate::Unsafe;
46    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
47    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
48}
49#[doc = "`reset()` method sets ICACHE_ATOMIC_OPERATE_ENA to value 0x01"]
50impl crate::Resettable for ICACHE_ATOMIC_OPERATE_ENA_SPEC {
51    const RESET_VALUE: u32 = 0x01;
52}
esp32s3/extmem/icache_atomic_operate_ena.rs

esp32s3/extmem/
icache_atomic_operate_ena.rs
