esp32s3/apb_saradc/
thres_ctrl.rs

1#[doc = "Register `THRES_CTRL` reader"]
2pub type R = crate::R<THRES_CTRL_SPEC>;
3#[doc = "Register `THRES_CTRL` writer"]
4pub type W = crate::W<THRES_CTRL_SPEC>;
5#[doc = "Field `THRES_ALL_EN` reader - enable thres0 to monitor all channel"]
6pub type THRES_ALL_EN_R = crate::BitReader;
7#[doc = "Field `THRES_ALL_EN` writer - enable thres0 to monitor all channel"]
8pub type THRES_ALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `THRES3_EN` reader - no public"]
10pub type THRES3_EN_R = crate::BitReader;
11#[doc = "Field `THRES3_EN` writer - no public"]
12pub type THRES3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `THRES2_EN` reader - no public"]
14pub type THRES2_EN_R = crate::BitReader;
15#[doc = "Field `THRES2_EN` writer - no public"]
16pub type THRES2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `THRES1_EN` reader - enable thres1"]
18pub type THRES1_EN_R = crate::BitReader;
19#[doc = "Field `THRES1_EN` writer - enable thres1"]
20pub type THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `THRES0_EN` reader - enable thres0"]
22pub type THRES0_EN_R = crate::BitReader;
23#[doc = "Field `THRES0_EN` writer - enable thres0"]
24pub type THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 27 - enable thres0 to monitor all channel"]
27    #[inline(always)]
28    pub fn thres_all_en(&self) -> THRES_ALL_EN_R {
29        THRES_ALL_EN_R::new(((self.bits >> 27) & 1) != 0)
30    }
31    #[doc = "Bit 28 - no public"]
32    #[inline(always)]
33    pub fn thres3_en(&self) -> THRES3_EN_R {
34        THRES3_EN_R::new(((self.bits >> 28) & 1) != 0)
35    }
36    #[doc = "Bit 29 - no public"]
37    #[inline(always)]
38    pub fn thres2_en(&self) -> THRES2_EN_R {
39        THRES2_EN_R::new(((self.bits >> 29) & 1) != 0)
40    }
41    #[doc = "Bit 30 - enable thres1"]
42    #[inline(always)]
43    pub fn thres1_en(&self) -> THRES1_EN_R {
44        THRES1_EN_R::new(((self.bits >> 30) & 1) != 0)
45    }
46    #[doc = "Bit 31 - enable thres0"]
47    #[inline(always)]
48    pub fn thres0_en(&self) -> THRES0_EN_R {
49        THRES0_EN_R::new(((self.bits >> 31) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("THRES_CTRL")
56            .field("thres_all_en", &self.thres_all_en())
57            .field("thres3_en", &self.thres3_en())
58            .field("thres2_en", &self.thres2_en())
59            .field("thres1_en", &self.thres1_en())
60            .field("thres0_en", &self.thres0_en())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 27 - enable thres0 to monitor all channel"]
66    #[inline(always)]
67    pub fn thres_all_en(&mut self) -> THRES_ALL_EN_W<THRES_CTRL_SPEC> {
68        THRES_ALL_EN_W::new(self, 27)
69    }
70    #[doc = "Bit 28 - no public"]
71    #[inline(always)]
72    pub fn thres3_en(&mut self) -> THRES3_EN_W<THRES_CTRL_SPEC> {
73        THRES3_EN_W::new(self, 28)
74    }
75    #[doc = "Bit 29 - no public"]
76    #[inline(always)]
77    pub fn thres2_en(&mut self) -> THRES2_EN_W<THRES_CTRL_SPEC> {
78        THRES2_EN_W::new(self, 29)
79    }
80    #[doc = "Bit 30 - enable thres1"]
81    #[inline(always)]
82    pub fn thres1_en(&mut self) -> THRES1_EN_W<THRES_CTRL_SPEC> {
83        THRES1_EN_W::new(self, 30)
84    }
85    #[doc = "Bit 31 - enable thres0"]
86    #[inline(always)]
87    pub fn thres0_en(&mut self) -> THRES0_EN_W<THRES_CTRL_SPEC> {
88        THRES0_EN_W::new(self, 31)
89    }
90}
91#[doc = "configure thres monitor enable\n\nYou can [`read`](crate::Reg::read) this register and get [`thres_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct THRES_CTRL_SPEC;
93impl crate::RegisterSpec for THRES_CTRL_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`thres_ctrl::R`](R) reader structure"]
97impl crate::Readable for THRES_CTRL_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`thres_ctrl::W`](W) writer structure"]
99impl crate::Writable for THRES_CTRL_SPEC {
100    type Safety = crate::Unsafe;
101    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
102    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103}
104#[doc = "`reset()` method sets THRES_CTRL to value 0"]
105impl crate::Resettable for THRES_CTRL_SPEC {
106    const RESET_VALUE: u32 = 0;
107}
esp32s3/apb_saradc/thres_ctrl.rs

esp32s3/apb_saradc/
thres_ctrl.rs
