esp32s3::spi1

Module ctrl1

Source
Expand description

SPI1 control1 register

Structs§

Type Aliases§

  • CLK_MODE_R
    Field CLK_MODE reader - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.
  • CLK_MODE_W
    Field CLK_MODE writer - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.
  • CS_HOLD_DLY_RES_R
    Field CS_HOLD_DLY_RES reader - After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.
  • CS_HOLD_DLY_RES_W
    Field CS_HOLD_DLY_RES writer - After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.
  • R
    Register CTRL1 reader
  • W
    Register CTRL1 writer