Enum Interrupt

#[repr(u16)]
pub enum Interrupt {
    WIFI_MAC = 0,
    WIFI_NMI = 1,
    WIFI_PWR = 2,
    WIFI_BB = 3,
    BT_MAC = 4,
    BT_BB = 5,
    BT_BB_NMI = 6,
    RWBT = 7,
    RWBLE = 8,
    RWBT_NMI = 9,
    RWBLE_NMI = 10,
    I2C_MASTER = 11,
    SLC0 = 12,
    SLC1 = 13,
    UHCI0 = 14,
    UHCI1 = 15,
    GPIO = 16,
    GPIO_NMI = 17,
    GPIO_INTR_2 = 18,
    GPIO_NMI_2 = 19,
    SPI1 = 20,
    SPI2 = 21,
    SPI3 = 22,
    LCD_CAM = 24,
    I2S0 = 25,
    I2S1 = 26,
    UART0 = 27,
    UART1 = 28,
    UART2 = 29,
    SDIO_HOST = 30,
    MCPWM0 = 31,
    MCPWM1 = 32,
    LEDC = 35,
    EFUSE = 36,
    TWAI0 = 37,
    USB = 38,
    RTC_CORE = 39,
    RMT = 40,
    PCNT = 41,
    I2C_EXT0 = 42,
    I2C_EXT1 = 43,
    SPI2_DMA = 44,
    SPI3_DMA = 45,
    WDT = 47,
    TIMER1 = 48,
    TIMER2 = 49,
    TG0_T0_LEVEL = 50,
    TG0_T1_LEVEL = 51,
    TG0_WDT_LEVEL = 52,
    TG1_T0_LEVEL = 53,
    TG1_T1_LEVEL = 54,
    TG1_WDT_LEVEL = 55,
    CACHE_IA = 56,
    SYSTIMER_TARGET0 = 57,
    SYSTIMER_TARGET1 = 58,
    SYSTIMER_TARGET2 = 59,
    SPI_MEM_REJECT_CACHE = 60,
    DCACHE_PRELOAD0 = 61,
    ICACHE_PRELOAD0 = 62,
    DCACHE_SYNC0 = 63,
    ICACHE_SYNC0 = 64,
    APB_ADC = 65,
    DMA_IN_CH0 = 66,
    DMA_IN_CH1 = 67,
    DMA_IN_CH2 = 68,
    DMA_IN_CH3 = 69,
    DMA_IN_CH4 = 70,
    DMA_OUT_CH0 = 71,
    DMA_OUT_CH1 = 72,
    DMA_OUT_CH2 = 73,
    DMA_OUT_CH3 = 74,
    DMA_OUT_CH4 = 75,
    RSA = 76,
    SHA = 77,
    FROM_CPU_INTR0 = 79,
    FROM_CPU_INTR1 = 80,
    FROM_CPU_INTR2 = 81,
    FROM_CPU_INTR3 = 82,
    ASSIST_DEBUG = 83,
    DMA_APBPERI_PMS = 84,
    CORE0_IRAM0_PMS = 85,
    CORE0_DRAM0_PMS = 86,
    CORE0_PIF_PMS = 87,
    CORE0_PIF_PMS_SIZE = 88,
    CORE1_IRAM0_PMS = 89,
    CORE1_DRAM0_PMS = 90,
    CORE1_PIF_PMS = 91,
    CORE1_PIF_PMS_SIZE = 92,
    BACKUP_PMS_VIOLATE = 93,
    CACHE_CORE0_ACS = 94,
    CACHE_CORE1_ACS = 95,
    USB_DEVICE = 96,
    PERI_BACKUP = 97,
    DMA_EXTMEM_REJECT = 98,
}

Enumeration of all the interrupts.

Variants

WIFI_MAC = 0

0 - WIFI_MAC

WIFI_NMI = 1

1 - WIFI_NMI

WIFI_PWR = 2

2 - WIFI_PWR

WIFI_BB = 3

3 - WIFI_BB

BT_MAC = 4

4 - BT_MAC

BT_BB = 5

5 - BT_BB

BT_BB_NMI = 6

6 - BT_BB_NMI

RWBT = 7

7 - RWBT

RWBLE = 8

8 - RWBLE

RWBT_NMI = 9

9 - RWBT_NMI

RWBLE_NMI = 10

10 - RWBLE_NMI

I2C_MASTER = 11

11 - I2C_MASTER

SLC0 = 12

12 - SLC0

SLC1 = 13

13 - SLC1

UHCI0 = 14

14 - UHCI0

UHCI1 = 15

15 - UHCI1

GPIO = 16

16 - GPIO

GPIO_NMI = 17

17 - GPIO_NMI

GPIO_INTR_2 = 18

18 - GPIO_INTR_2

GPIO_NMI_2 = 19

19 - GPIO_NMI_2

SPI1 = 20

20 - SPI1

SPI2 = 21

21 - SPI2

SPI3 = 22

22 - SPI3

LCD_CAM = 24

24 - LCD_CAM

I2S0 = 25

25 - I2S0

I2S1 = 26

26 - I2S1

UART0 = 27

27 - UART0

UART1 = 28

28 - UART1

UART2 = 29

29 - UART2

SDIO_HOST = 30

30 - SDIO_HOST

MCPWM0 = 31

31 - MCPWM0

MCPWM1 = 32

32 - MCPWM1

LEDC = 35

35 - LEDC

EFUSE = 36

36 - EFUSE

TWAI0 = 37

37 - TWAI0

USB = 38

38 - USB

RTC_CORE = 39

39 - RTC_CORE

RMT = 40

40 - RMT

PCNT = 41

41 - PCNT

I2C_EXT0 = 42

42 - I2C_EXT0

I2C_EXT1 = 43

43 - I2C_EXT1

SPI2_DMA = 44

44 - SPI2_DMA

SPI3_DMA = 45

45 - SPI3_DMA

WDT = 47

47 - WDT

TIMER1 = 48

48 - TIMER1

TIMER2 = 49

49 - TIMER2

TG0_T0_LEVEL = 50

50 - TG0_T0_LEVEL

TG0_T1_LEVEL = 51

51 - TG0_T1_LEVEL

TG0_WDT_LEVEL = 52

52 - TG0_WDT_LEVEL

TG1_T0_LEVEL = 53

53 - TG1_T0_LEVEL

TG1_T1_LEVEL = 54

54 - TG1_T1_LEVEL

TG1_WDT_LEVEL = 55

55 - TG1_WDT_LEVEL

CACHE_IA = 56

56 - CACHE_IA

SYSTIMER_TARGET0 = 57

57 - SYSTIMER_TARGET0

SYSTIMER_TARGET1 = 58

58 - SYSTIMER_TARGET1

SYSTIMER_TARGET2 = 59

59 - SYSTIMER_TARGET2

SPI_MEM_REJECT_CACHE = 60

60 - SPI_MEM_REJECT_CACHE

DCACHE_PRELOAD0 = 61

61 - DCACHE_PRELOAD0

ICACHE_PRELOAD0 = 62

62 - ICACHE_PRELOAD0

DCACHE_SYNC0 = 63

63 - DCACHE_SYNC0

ICACHE_SYNC0 = 64

64 - ICACHE_SYNC0

APB_ADC = 65

65 - APB_ADC

DMA_IN_CH0 = 66

66 - DMA_IN_CH0

DMA_IN_CH1 = 67

67 - DMA_IN_CH1

DMA_IN_CH2 = 68

68 - DMA_IN_CH2

DMA_IN_CH3 = 69

69 - DMA_IN_CH3

DMA_IN_CH4 = 70

70 - DMA_IN_CH4

DMA_OUT_CH0 = 71

71 - DMA_OUT_CH0

DMA_OUT_CH1 = 72

72 - DMA_OUT_CH1

DMA_OUT_CH2 = 73

73 - DMA_OUT_CH2

DMA_OUT_CH3 = 74

74 - DMA_OUT_CH3

DMA_OUT_CH4 = 75

75 - DMA_OUT_CH4

RSA = 76

76 - RSA

SHA = 77

77 - SHA

FROM_CPU_INTR0 = 79

79 - FROM_CPU_INTR0

FROM_CPU_INTR1 = 80

80 - FROM_CPU_INTR1

FROM_CPU_INTR2 = 81

81 - FROM_CPU_INTR2

FROM_CPU_INTR3 = 82

82 - FROM_CPU_INTR3

ASSIST_DEBUG = 83

83 - ASSIST_DEBUG

DMA_APBPERI_PMS = 84

84 - DMA_APBPERI_PMS

CORE0_IRAM0_PMS = 85

85 - CORE0_IRAM0_PMS

CORE0_DRAM0_PMS = 86

86 - CORE0_DRAM0_PMS

CORE0_PIF_PMS = 87

87 - CORE0_PIF_PMS

CORE0_PIF_PMS_SIZE = 88

88 - CORE0_PIF_PMS_SIZE

CORE1_IRAM0_PMS = 89

89 - CORE1_IRAM0_PMS

CORE1_DRAM0_PMS = 90

90 - CORE1_DRAM0_PMS

CORE1_PIF_PMS = 91

91 - CORE1_PIF_PMS

CORE1_PIF_PMS_SIZE = 92

92 - CORE1_PIF_PMS_SIZE

BACKUP_PMS_VIOLATE = 93

93 - BACKUP_PMS_VIOLATE

CACHE_CORE0_ACS = 94

94 - CACHE_CORE0_ACS

CACHE_CORE1_ACS = 95

95 - CACHE_CORE1_ACS

USB_DEVICE = 96

96 - USB_DEVICE

PERI_BACKUP = 97

97 - PERI_BACKUP

DMA_EXTMEM_REJECT = 98

98 - DMA_EXTMEM_REJECT

Implementations

impl Interrupt

pub fn try_from(value: u16) -> Result<Self, TryFromInterruptError>

Attempt to convert a given value into an Interrupt

Trait Implementations

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Interrupt

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Interrupt

impl Eq for Interrupt

impl StructuralPartialEq for Interrupt