Struct esp32s3::spi0::cache_sctrl::CACHE_SCTRL_SPEC
source · [−]pub struct CACHE_SCTRL_SPEC;
Expand description
SPI0 external RAM control register
This register you can read
, write_with_zero
, reset
, write
, modify
. See API.
For information about available fields see cache_sctrl module
Trait Implementations
sourceimpl Readable for CACHE_SCTRL_SPEC
impl Readable for CACHE_SCTRL_SPEC
read()
method returns cache_sctrl::R reader structure
sourceimpl RegisterSpec for CACHE_SCTRL_SPEC
impl RegisterSpec for CACHE_SCTRL_SPEC
sourceimpl Resettable for CACHE_SCTRL_SPEC
impl Resettable for CACHE_SCTRL_SPEC
reset()
method sets CACHE_SCTRL to value 0x0055_c070
sourcefn reset_value() -> Self::Ux
fn reset_value() -> Self::Ux
Reset value of the register.
sourceimpl Writable for CACHE_SCTRL_SPEC
impl Writable for CACHE_SCTRL_SPEC
write(|w| ..)
method takes cache_sctrl::W writer structure
Auto Trait Implementations
impl RefUnwindSafe for CACHE_SCTRL_SPEC
impl Send for CACHE_SCTRL_SPEC
impl Sync for CACHE_SCTRL_SPEC
impl Unpin for CACHE_SCTRL_SPEC
impl UnwindSafe for CACHE_SCTRL_SPEC
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more