#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_7` reader"]
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>;
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_7` writer"]
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` reader - Core0 access spi_2 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` writer - Core0 access spi_2 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` reader - Core0 access spi_3 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` writer - Core0 access spi_3 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` reader - Core0 access apb_ctrl permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` writer - Core0 access apb_ctrl permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` reader - Core0 access i2c_ext1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` writer - Core0 access i2c_ext1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` reader - Core0 access sdio_host permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` writer - Core0 access sdio_host permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN` reader - Core0 access can permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN` writer - Core0 access can permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` reader - Core0 access pwm1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` writer - Core0 access pwm1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` reader - Core0 access i2s1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` writer - Core0 access i2s1 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2` reader - Core0 access uart2 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2` writer - Core0 access uart2 permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` reader - Core0 access rwbt permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` writer - Core0 access rwbt permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` reader - Core0 access wifimac permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` writer - Core0 access wifimac permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR` reader - Core0 access pwr permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R = crate::FieldReader;
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR` writer - Core0 access pwr permission in world1."]
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
impl R {
    #[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_spi_2(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R::new((self.bits & 3) as u8)
    }
    #[doc = "Bits 2:3 - Core0 access spi_3 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_spi_3(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
    }
    #[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_apb_ctrl(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
    }
    #[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_i2c_ext1(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
    }
    #[doc = "Bits 8:9 - Core0 access sdio_host permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_sdio_host(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
    }
    #[doc = "Bits 10:11 - Core0 access can permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_can(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R::new(((self.bits >> 10) & 3) as u8)
    }
    #[doc = "Bits 12:13 - Core0 access pwm1 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_pwm1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R::new(((self.bits >> 12) & 3) as u8)
    }
    #[doc = "Bits 14:15 - Core0 access i2s1 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_i2s1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R::new(((self.bits >> 14) & 3) as u8)
    }
    #[doc = "Bits 16:17 - Core0 access uart2 permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_uart2(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R::new(((self.bits >> 16) & 3) as u8)
    }
    #[doc = "Bits 22:23 - Core0 access rwbt permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_rwbt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R::new(((self.bits >> 22) & 3) as u8)
    }
    #[doc = "Bits 26:27 - Core0 access wifimac permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_wifimac(
        &self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
    }
    #[doc = "Bits 28:29 - Core0 access pwr permission in world1."]
    #[inline(always)]
    pub fn core_0_pif_pms_constrain_world_1_pwr(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R::new(((self.bits >> 28) & 3) as u8)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_7")
            .field(
                "core_0_pif_pms_constrain_world_1_spi_2",
                &self.core_0_pif_pms_constrain_world_1_spi_2(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_spi_3",
                &self.core_0_pif_pms_constrain_world_1_spi_3(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_apb_ctrl",
                &self.core_0_pif_pms_constrain_world_1_apb_ctrl(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_i2c_ext1",
                &self.core_0_pif_pms_constrain_world_1_i2c_ext1(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_sdio_host",
                &self.core_0_pif_pms_constrain_world_1_sdio_host(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_can",
                &self.core_0_pif_pms_constrain_world_1_can(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_pwm1",
                &self.core_0_pif_pms_constrain_world_1_pwm1(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_i2s1",
                &self.core_0_pif_pms_constrain_world_1_i2s1(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_uart2",
                &self.core_0_pif_pms_constrain_world_1_uart2(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_rwbt",
                &self.core_0_pif_pms_constrain_world_1_rwbt(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_wifimac",
                &self.core_0_pif_pms_constrain_world_1_wifimac(),
            )
            .field(
                "core_0_pif_pms_constrain_world_1_pwr",
                &self.core_0_pif_pms_constrain_world_1_pwr(),
            )
            .finish()
    }
}
impl W {
    #[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_spi_2(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W::new(self, 0)
    }
    #[doc = "Bits 2:3 - Core0 access spi_3 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_spi_3(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W::new(self, 2)
    }
    #[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_apb_ctrl(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W::new(self, 4)
    }
    #[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_i2c_ext1(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W::new(self, 6)
    }
    #[doc = "Bits 8:9 - Core0 access sdio_host permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_sdio_host(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W::new(self, 8)
    }
    #[doc = "Bits 10:11 - Core0 access can permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_can(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W::new(self, 10)
    }
    #[doc = "Bits 12:13 - Core0 access pwm1 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_pwm1(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W::new(self, 12)
    }
    #[doc = "Bits 14:15 - Core0 access i2s1 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_i2s1(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W::new(self, 14)
    }
    #[doc = "Bits 16:17 - Core0 access uart2 permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_uart2(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W::new(self, 16)
    }
    #[doc = "Bits 22:23 - Core0 access rwbt permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_rwbt(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W::new(self, 22)
    }
    #[doc = "Bits 26:27 - Core0 access wifimac permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_wifimac(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W::new(self, 26)
    }
    #[doc = "Bits 28:29 - Core0 access pwr permission in world1."]
    #[inline(always)]
    #[must_use]
    pub fn core_0_pif_pms_constrain_world_1_pwr(
        &mut self,
    ) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
        CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W::new(self, 28)
    }
}
#[doc = "Core0 access peripherals permission configuration register 7.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CORE_0_PIF_PMS_CONSTRAIN_7_SPEC;
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_7::R`](R) reader structure"]
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {}
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_7::W`](W) writer structure"]
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_7 to value 0x3cc3_ffff"]
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
    const RESET_VALUE: u32 = 0x3cc3_ffff;
}