Type Alias esp32s3::spi0::ctrl2::R

pub type R = R<CTRL2_SPEC>;

Register CTRL2 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R

Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.

pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R

Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.

pub fn ecc_cs_hold_time(&self) -> ECC_CS_HOLD_TIME_R

Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.

pub fn ecc_skip_page_corner(&self) -> ECC_SKIP_PAGE_CORNER_R

Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.

pub fn ecc_16to18_byte_en(&self) -> ECC_16TO18_BYTE_EN_R

Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

pub fn sync_reset(&self) -> SYNC_RESET_R

Bit 31 - The FSM will be reset.