Module esp32s3::spi0::cache_fctrl

SPI0 external RAM bit mode control register.

Structs

• CACHE_FCTRL_SPEC
  SPI0 external RAM bit mode control register.

Type Aliases

• CACHE_FLASH_USR_CMD_R
  Field CACHE_FLASH_USR_CMD reader - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.
• CACHE_FLASH_USR_CMD_W
  Field CACHE_FLASH_USR_CMD writer - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.
• CACHE_REQ_EN_R
  Field CACHE_REQ_EN reader - Set this bit to enable Cache’s access and SPI0’s transfer.
• CACHE_REQ_EN_W
  Field CACHE_REQ_EN writer - Set this bit to enable Cache’s access and SPI0’s transfer.
• CACHE_USR_CMD_4BYTE_R
  Field CACHE_USR_CMD_4BYTE reader - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
• CACHE_USR_CMD_4BYTE_W
  Field CACHE_USR_CMD_4BYTE writer - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
• FADDR_DUAL_R
  Field FADDR_DUAL reader - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.
• FADDR_DUAL_W
  Field FADDR_DUAL writer - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.
• FADDR_QUAD_R
  Field FADDR_QUAD reader - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.
• FADDR_QUAD_W
  Field FADDR_QUAD writer - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.
• FDIN_DUAL_R
  Field FDIN_DUAL reader - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.
• FDIN_DUAL_W
  Field FDIN_DUAL writer - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.
• FDIN_QUAD_R
  Field FDIN_QUAD reader - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.
• FDIN_QUAD_W
  Field FDIN_QUAD writer - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.
• FDOUT_DUAL_R
  Field FDOUT_DUAL reader - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.
• FDOUT_DUAL_W
  Field FDOUT_DUAL writer - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.
• FDOUT_QUAD_R
  Field FDOUT_QUAD reader - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.
• FDOUT_QUAD_W
  Field FDOUT_QUAD writer - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.
• R
  Register CACHE_FCTRL reader
• W
  Register CACHE_FCTRL writer