Module esp32s3::i2c0::fifo_conf

FIFO configuration register.

Structs

• FIFO_CONF_SPEC
  FIFO configuration register.

Type Aliases

• FIFO_ADDR_CFG_EN_R
  Field FIFO_ADDR_CFG_EN reader - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.
• FIFO_ADDR_CFG_EN_W
  Field FIFO_ADDR_CFG_EN writer - When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM.
• FIFO_PRT_EN_R
  Field FIFO_PRT_EN reader - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
• FIFO_PRT_EN_W
  Field FIFO_PRT_EN writer - The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
• NONFIFO_EN_R
  Field NONFIFO_EN reader - Set this bit to enable APB nonfifo access.
• NONFIFO_EN_W
  Field NONFIFO_EN writer - Set this bit to enable APB nonfifo access.
• R
  Register FIFO_CONF reader
• RXFIFO_WM_THRHD_R
  Field RXFIFO_WM_THRHD reader - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
• RXFIFO_WM_THRHD_W
  Field RXFIFO_WM_THRHD writer - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
• RX_FIFO_RST_R
  Field RX_FIFO_RST reader - Set this bit to reset rx-fifo.
• RX_FIFO_RST_W
  Field RX_FIFO_RST writer - Set this bit to reset rx-fifo.
• TXFIFO_WM_THRHD_R
  Field TXFIFO_WM_THRHD reader - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
• TXFIFO_WM_THRHD_W
  Field TXFIFO_WM_THRHD writer - The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
• TX_FIFO_RST_R
  Field TX_FIFO_RST reader - Set this bit to reset tx-fifo.
• TX_FIFO_RST_W
  Field TX_FIFO_RST writer - Set this bit to reset tx-fifo.
• W
  Register FIFO_CONF writer