Module esp32s3::apb_saradc::ctrl

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configure apb saradc controller

Structs§

Type Aliases§

  • DATA_SAR_SEL_R
    Field DATA_SAR_SEL reader - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.
  • DATA_SAR_SEL_W
    Field DATA_SAR_SEL writer - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.
  • DATA_TO_I2S_R
    Field DATA_TO_I2S reader - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
  • DATA_TO_I2S_W
    Field DATA_TO_I2S writer - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
  • R
    Register CTRL reader
  • SAR1_PATT_LEN_R
    Field SAR1_PATT_LEN reader - 0 ~ 15 means length 1 ~ 16
  • SAR1_PATT_LEN_W
    Field SAR1_PATT_LEN writer - 0 ~ 15 means length 1 ~ 16
  • SAR1_PATT_P_CLEAR_R
    Field SAR1_PATT_P_CLEAR reader - clear the pointer of pattern table for DIG ADC1 CTRL
  • SAR1_PATT_P_CLEAR_W
    Field SAR1_PATT_P_CLEAR writer - clear the pointer of pattern table for DIG ADC1 CTRL
  • SAR2_PATT_LEN_R
    Field SAR2_PATT_LEN reader - 0 ~ 15 means length 1 ~ 16
  • SAR2_PATT_LEN_W
    Field SAR2_PATT_LEN writer - 0 ~ 15 means length 1 ~ 16
  • SAR2_PATT_P_CLEAR_R
    Field SAR2_PATT_P_CLEAR reader - clear the pointer of pattern table for DIG ADC2 CTRL
  • SAR2_PATT_P_CLEAR_W
    Field SAR2_PATT_P_CLEAR writer - clear the pointer of pattern table for DIG ADC2 CTRL
  • SAR_CLK_DIV_R
    Field SAR_CLK_DIV reader - SAR clock divider
  • SAR_CLK_DIV_W
    Field SAR_CLK_DIV writer - SAR clock divider
  • SAR_CLK_GATED_R
    Field SAR_CLK_GATED reader - enable SAR CLK gate when saradc idle
  • SAR_CLK_GATED_W
    Field SAR_CLK_GATED writer - enable SAR CLK gate when saradc idle
  • SAR_SEL_R
    Field SAR_SEL reader - 0: SAR1, 1: SAR2, only work for single SAR mode
  • SAR_SEL_W
    Field SAR_SEL writer - 0: SAR1, 1: SAR2, only work for single SAR mode
  • START_FORCE_R
    Field START_FORCE reader - enable start saradc by sw
  • START_FORCE_W
    Field START_FORCE writer - enable start saradc by sw
  • START_R
    Field START reader - start saradc by sw
  • START_W
    Field START writer - start saradc by sw
  • W
    Register CTRL writer
  • WAIT_ARB_CYCLE_R
    Field WAIT_ARB_CYCLE reader - wait arbit signal stable after sar_done
  • WAIT_ARB_CYCLE_W
    Field WAIT_ARB_CYCLE writer - wait arbit signal stable after sar_done
  • WORK_MODE_R
    Field WORK_MODE reader - 0: single mode, 1: double mode, 2: alternate mode
  • WORK_MODE_W
    Field WORK_MODE writer - 0: single mode, 1: double mode, 2: alternate mode
  • XPD_SAR_FORCE_R
    Field XPD_SAR_FORCE reader - force option to xpd sar blocks
  • XPD_SAR_FORCE_W
    Field XPD_SAR_FORCE writer - force option to xpd sar blocks