Type Alias esp32s3::rmt::int_clr::W

pub type W = W<INT_CLR_SPEC>;

Register INT_CLR writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH(0-3)_TX_END_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_END field

pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt.

pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt.

pub fn ch2_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt.

pub fn ch3_tx_end(&mut self) -> CH_TX_END_W<'_, INT_CLR_SPEC>

Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt.

pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH(0-3)_ERR_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_ERR field

pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt.

pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt.

pub fn ch2_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt.

pub fn ch3_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_CLR_SPEC>

Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt.

pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH(0-3)_TX_THR_EVENT_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_THR_EVENT field

pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.

pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.

pub fn ch2_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt.

pub fn ch3_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt.

pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH(0-3)_TX_LOOP_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH0_TX_LOOP field

pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt.

pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt.

pub fn ch2_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt.

pub fn ch3_tx_loop(&mut self) -> CH_TX_LOOP_W<'_, INT_CLR_SPEC>

Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt.

pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH4_RX_END_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH4_RX_END field

pub fn ch4_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt.

pub fn ch5_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 17 - Set this bit to clear theCH4_RX_END_INT interrupt.

pub fn ch6_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 18 - Set this bit to clear theCH4_RX_END_INT interrupt.

pub fn ch7_rx_end(&mut self) -> CH_RX_END_W<'_, INT_CLR_SPEC>

Bit 19 - Set this bit to clear theCH4_RX_END_INT interrupt.

pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH4_ERR_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH4_RX_ERR field

pub fn ch4_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt.

pub fn ch5_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 21 - Set this bit to clear theCH4_ERR_INT interrupt.

pub fn ch6_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 22 - Set this bit to clear theCH4_ERR_INT interrupt.

pub fn ch7_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_CLR_SPEC>

Bit 23 - Set this bit to clear theCH4_ERR_INT interrupt.

pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.

NOTE: n is number of field in register. n == 0 corresponds to CH4_RX_THR_EVENT field

pub fn ch4_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.

pub fn ch5_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 25 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.

pub fn ch6_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 26 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.

pub fn ch7_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_CLR_SPEC>

Bit 27 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.

pub fn tx_ch3_dma_access_fail( &mut self ) -> TX_CH3_DMA_ACCESS_FAIL_W<'_, INT_CLR_SPEC>

Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.

pub fn rx_ch7_dma_access_fail( &mut self ) -> RX_CH7_DMA_ACCESS_FAIL_W<'_, INT_CLR_SPEC>

Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual