Type Alias esp32s3::uart0::int_ena::W

pub type W = W<INT_ENA_SPEC>;

Register INT_ENA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn rxfifo_full_int_ena( &mut self ) -> RXFIFO_FULL_INT_ENA_W<'_, INT_ENA_SPEC, 0>

Bit 0 - This is the enable bit for rxfifo_full_int_st register.

pub fn txfifo_empty_int_ena( &mut self ) -> TXFIFO_EMPTY_INT_ENA_W<'_, INT_ENA_SPEC, 1>

Bit 1 - This is the enable bit for txfifo_empty_int_st register.

pub fn parity_err_int_ena( &mut self ) -> PARITY_ERR_INT_ENA_W<'_, INT_ENA_SPEC, 2>

Bit 2 - This is the enable bit for parity_err_int_st register.

pub fn frm_err_int_ena(&mut self) -> FRM_ERR_INT_ENA_W<'_, INT_ENA_SPEC, 3>

Bit 3 - This is the enable bit for frm_err_int_st register.

pub fn rxfifo_ovf_int_ena( &mut self ) -> RXFIFO_OVF_INT_ENA_W<'_, INT_ENA_SPEC, 4>

Bit 4 - This is the enable bit for rxfifo_ovf_int_st register.

pub fn dsr_chg_int_ena(&mut self) -> DSR_CHG_INT_ENA_W<'_, INT_ENA_SPEC, 5>

Bit 5 - This is the enable bit for dsr_chg_int_st register.

pub fn cts_chg_int_ena(&mut self) -> CTS_CHG_INT_ENA_W<'_, INT_ENA_SPEC, 6>

Bit 6 - This is the enable bit for cts_chg_int_st register.

pub fn brk_det_int_ena(&mut self) -> BRK_DET_INT_ENA_W<'_, INT_ENA_SPEC, 7>

Bit 7 - This is the enable bit for brk_det_int_st register.

pub fn rxfifo_tout_int_ena( &mut self ) -> RXFIFO_TOUT_INT_ENA_W<'_, INT_ENA_SPEC, 8>

Bit 8 - This is the enable bit for rxfifo_tout_int_st register.

pub fn sw_xon_int_ena(&mut self) -> SW_XON_INT_ENA_W<'_, INT_ENA_SPEC, 9>

Bit 9 - This is the enable bit for sw_xon_int_st register.

pub fn sw_xoff_int_ena(&mut self) -> SW_XOFF_INT_ENA_W<'_, INT_ENA_SPEC, 10>

Bit 10 - This is the enable bit for sw_xoff_int_st register.

pub fn glitch_det_int_ena( &mut self ) -> GLITCH_DET_INT_ENA_W<'_, INT_ENA_SPEC, 11>

Bit 11 - This is the enable bit for glitch_det_int_st register.

pub fn tx_brk_done_int_ena( &mut self ) -> TX_BRK_DONE_INT_ENA_W<'_, INT_ENA_SPEC, 12>

Bit 12 - This is the enable bit for tx_brk_done_int_st register.

pub fn tx_brk_idle_done_int_ena( &mut self ) -> TX_BRK_IDLE_DONE_INT_ENA_W<'_, INT_ENA_SPEC, 13>

Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register.

pub fn tx_done_int_ena(&mut self) -> TX_DONE_INT_ENA_W<'_, INT_ENA_SPEC, 14>

Bit 14 - This is the enable bit for tx_done_int_st register.

pub fn rs485_parity_err_int_ena( &mut self ) -> RS485_PARITY_ERR_INT_ENA_W<'_, INT_ENA_SPEC, 15>

Bit 15 - This is the enable bit for rs485_parity_err_int_st register.

pub fn rs485_frm_err_int_ena( &mut self ) -> RS485_FRM_ERR_INT_ENA_W<'_, INT_ENA_SPEC, 16>

Bit 16 - This is the enable bit for rs485_parity_err_int_st register.

pub fn rs485_clash_int_ena( &mut self ) -> RS485_CLASH_INT_ENA_W<'_, INT_ENA_SPEC, 17>

Bit 17 - This is the enable bit for rs485_clash_int_st register.

pub fn at_cmd_char_det_int_ena( &mut self ) -> AT_CMD_CHAR_DET_INT_ENA_W<'_, INT_ENA_SPEC, 18>

Bit 18 - This is the enable bit for at_cmd_char_det_int_st register.

pub fn wakeup_int_ena(&mut self) -> WAKEUP_INT_ENA_W<'_, INT_ENA_SPEC, 19>

Bit 19 - This is the enable bit for uart_wakeup_int_st register.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual