Struct esp32s3::assist_debug::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 87 fields
    pub core_0_montr_ena: CORE_0_MONTR_ENA,
    pub core_0_intr_raw: CORE_0_INTR_RAW,
    pub core_0_intr_ena: CORE_0_INTR_ENA,
    pub core_0_intr_clr: CORE_0_INTR_CLR,
    pub core_0_area_dram0_0_min: CORE_0_AREA_DRAM0_0_MIN,
    pub core_0_area_dram0_0_max: CORE_0_AREA_DRAM0_0_MAX,
    pub core_0_area_dram0_1_min: CORE_0_AREA_DRAM0_1_MIN,
    pub core_0_area_dram0_1_max: CORE_0_AREA_DRAM0_1_MAX,
    pub core_0_area_pif_0_min: CORE_0_AREA_PIF_0_MIN,
    pub core_0_area_pif_0_max: CORE_0_AREA_PIF_0_MAX,
    pub core_0_area_pif_1_min: CORE_0_AREA_PIF_1_MIN,
    pub core_0_area_pif_1_max: CORE_0_AREA_PIF_1_MAX,
    pub core_0_area_sp: CORE_0_AREA_SP,
    pub core_0_area_pc: CORE_0_AREA_PC,
    pub core_0_sp_unstable: CORE_0_SP_UNSTABLE,
    pub core_0_sp_min: CORE_0_SP_MIN,
    pub core_0_sp_max: CORE_0_SP_MAX,
    pub core_0_sp_pc: CORE_0_SP_PC,
    pub core_0_rcd_pdebugenable: CORE_0_RCD_PDEBUGENABLE,
    pub core_0_rcd_recording: CORE_0_RCD_RECORDING,
    pub core_0_rcd_pdebuginst: CORE_0_RCD_PDEBUGINST,
    pub core_0_rcd_pdebugstatus: CORE_0_RCD_PDEBUGSTATUS,
    pub core_0_rcd_pdebugdata: CORE_0_RCD_PDEBUGDATA,
    pub core_0_rcd_pdebugpc: CORE_0_RCD_PDEBUGPC,
    pub core_0_rcd_pdebugls0stat: CORE_0_RCD_PDEBUGLS0STAT,
    pub core_0_rcd_pdebugls0addr: CORE_0_RCD_PDEBUGLS0ADDR,
    pub core_0_rcd_pdebugls0data: CORE_0_RCD_PDEBUGLS0DATA,
    pub core_0_rcd_sp: CORE_0_RCD_SP,
    pub core_0_iram0_exception_monitor_0: CORE_0_IRAM0_EXCEPTION_MONITOR_0,
    pub core_0_iram0_exception_monitor_1: CORE_0_IRAM0_EXCEPTION_MONITOR_1,
    pub core_0_dram0_exception_monitor_0: CORE_0_DRAM0_EXCEPTION_MONITOR_0,
    pub core_0_dram0_exception_monitor_1: CORE_0_DRAM0_EXCEPTION_MONITOR_1,
    pub core_0_dram0_exception_monitor_2: CORE_0_DRAM0_EXCEPTION_MONITOR_2,
    pub core_0_dram0_exception_monitor_3: CORE_0_DRAM0_EXCEPTION_MONITOR_3,
    pub core_0_dram0_exception_monitor_4: CORE_0_DRAM0_EXCEPTION_MONITOR_4,
    pub core_0_dram0_exception_monitor_5: CORE_0_DRAM0_EXCEPTION_MONITOR_5,
    pub core_1_montr_ena: CORE_1_MONTR_ENA,
    pub core_1_intr_raw: CORE_1_INTR_RAW,
    pub core_1_intr_ena: CORE_1_INTR_ENA,
    pub core_1_intr_clr: CORE_1_INTR_CLR,
    pub core_1_area_dram0_0_min: CORE_1_AREA_DRAM0_0_MIN,
    pub core_1_area_dram0_0_max: CORE_1_AREA_DRAM0_0_MAX,
    pub core_1_area_dram0_1_min: CORE_1_AREA_DRAM0_1_MIN,
    pub core_1_area_dram0_1_max: CORE_1_AREA_DRAM0_1_MAX,
    pub core_1_area_pif_0_min: CORE_1_AREA_PIF_0_MIN,
    pub core_1_area_pif_0_max: CORE_1_AREA_PIF_0_MAX,
    pub core_1_area_pif_1_min: CORE_1_AREA_PIF_1_MIN,
    pub core_1_area_pif_1_max: CORE_1_AREA_PIF_1_MAX,
    pub core_1_area_pc: CORE_1_AREA_PC,
    pub core_1_area_sp: CORE_1_AREA_SP,
    pub core_1_sp_unstable: CORE_1_SP_UNSTABLE,
    pub core_1_sp_min: CORE_1_SP_MIN,
    pub core_1_sp_max: CORE_1_SP_MAX,
    pub core_1_sp_pc: CORE_1_SP_PC,
    pub core_1_rcd_pdebugenable: CORE_1_RCD_PDEBUGENABLE,
    pub core_1_rcd_recording: CORE_1_RCD_RECORDING,
    pub core_1_rcd_pdebuginst: CORE_1_RCD_PDEBUGINST,
    pub core_1_rcd_pdebugstatus: CORE_1_RCD_PDEBUGSTATUS,
    pub core_1_rcd_pdebugdata: CORE_1_RCD_PDEBUGDATA,
    pub core_1_rcd_pdebugpc: CORE_1_RCD_PDEBUGPC,
    pub core_1_rcd_pdebugls0stat: CORE_1_RCD_PDEBUGLS0STAT,
    pub core_1_rcd_pdebugls0addr: CORE_1_RCD_PDEBUGLS0ADDR,
    pub core_1_rcd_pdebugls0data: CORE_1_RCD_PDEBUGLS0DATA,
    pub core_1_rcd_sp: CORE_1_RCD_SP,
    pub core_1_iram0_exception_monitor_0: CORE_1_IRAM0_EXCEPTION_MONITOR_0,
    pub core_1_iram0_exception_monitor_1: CORE_1_IRAM0_EXCEPTION_MONITOR_1,
    pub core_1_dram0_exception_monitor_0: CORE_1_DRAM0_EXCEPTION_MONITOR_0,
    pub core_1_dram0_exception_monitor_1: CORE_1_DRAM0_EXCEPTION_MONITOR_1,
    pub core_1_dram0_exception_monitor_2: CORE_1_DRAM0_EXCEPTION_MONITOR_2,
    pub core_1_dram0_exception_monitor_3: CORE_1_DRAM0_EXCEPTION_MONITOR_3,
    pub core_1_dram0_exception_monitor_4: CORE_1_DRAM0_EXCEPTION_MONITOR_4,
    pub core_1_dram0_exception_monitor_5: CORE_1_DRAM0_EXCEPTION_MONITOR_5,
    pub core_x_iram0_dram0_exception_monitor_0: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0,
    pub core_x_iram0_dram0_exception_monitor_1: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1,
    pub log_setting: LOG_SETTING,
    pub log_data_0: LOG_DATA_0,
    pub log_data_1: LOG_DATA_1,
    pub log_data_2: LOG_DATA_2,
    pub log_data_3: LOG_DATA_3,
    pub log_data_mask: LOG_DATA_MASK,
    pub log_min: LOG_MIN,
    pub log_max: LOG_MAX,
    pub log_mem_start: LOG_MEM_START,
    pub log_mem_end: LOG_MEM_END,
    pub log_mem_writing_addr: LOG_MEM_WRITING_ADDR,
    pub log_mem_full_flag: LOG_MEM_FULL_FLAG,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§core_0_montr_ena: CORE_0_MONTR_ENA

0x00 - core0 monitor enable configuration register

§core_0_intr_raw: CORE_0_INTR_RAW

0x04 - core0 monitor interrupt status register

§core_0_intr_ena: CORE_0_INTR_ENA

0x08 - core0 monitor interrupt enable register

§core_0_intr_clr: CORE_0_INTR_CLR

0x0c - core0 monitor interrupt clr register

§core_0_area_dram0_0_min: CORE_0_AREA_DRAM0_0_MIN

0x10 - core0 dram0 region0 addr configuration register

§core_0_area_dram0_0_max: CORE_0_AREA_DRAM0_0_MAX

0x14 - core0 dram0 region0 addr configuration register

§core_0_area_dram0_1_min: CORE_0_AREA_DRAM0_1_MIN

0x18 - core0 dram0 region1 addr configuration register

§core_0_area_dram0_1_max: CORE_0_AREA_DRAM0_1_MAX

0x1c - core0 dram0 region1 addr configuration register

§core_0_area_pif_0_min: CORE_0_AREA_PIF_0_MIN

0x20 - core0 PIF region0 addr configuration register

§core_0_area_pif_0_max: CORE_0_AREA_PIF_0_MAX

0x24 - core0 PIF region0 addr configuration register

§core_0_area_pif_1_min: CORE_0_AREA_PIF_1_MIN

0x28 - core0 PIF region1 addr configuration register

§core_0_area_pif_1_max: CORE_0_AREA_PIF_1_MAX

0x2c - core0 PIF region1 addr configuration register

§core_0_area_sp: CORE_0_AREA_SP

0x30 - core0 area sp status register

§core_0_area_pc: CORE_0_AREA_PC

0x34 - core0 area pc status register

§core_0_sp_unstable: CORE_0_SP_UNSTABLE

0x38 - core0 sp unstable configuration register

§core_0_sp_min: CORE_0_SP_MIN

0x3c - core0 sp region configuration regsiter

§core_0_sp_max: CORE_0_SP_MAX

0x40 - core0 sp region configuration regsiter

§core_0_sp_pc: CORE_0_SP_PC

0x44 - core0 sp pc status register

§core_0_rcd_pdebugenable: CORE_0_RCD_PDEBUGENABLE

0x48 - core0 pdebug configuration register

§core_0_rcd_recording: CORE_0_RCD_RECORDING

0x4c - core0 pdebug status register

§core_0_rcd_pdebuginst: CORE_0_RCD_PDEBUGINST

0x50 - core0 pdebug status register

§core_0_rcd_pdebugstatus: CORE_0_RCD_PDEBUGSTATUS

0x54 - core0 pdebug status register

§core_0_rcd_pdebugdata: CORE_0_RCD_PDEBUGDATA

0x58 - core0 pdebug status register

§core_0_rcd_pdebugpc: CORE_0_RCD_PDEBUGPC

0x5c - core0 pdebug status register

§core_0_rcd_pdebugls0stat: CORE_0_RCD_PDEBUGLS0STAT

0x60 - core0 pdebug status register

§core_0_rcd_pdebugls0addr: CORE_0_RCD_PDEBUGLS0ADDR

0x64 - core0 pdebug status register

§core_0_rcd_pdebugls0data: CORE_0_RCD_PDEBUGLS0DATA

0x68 - core0 pdebug status register

§core_0_rcd_sp: CORE_0_RCD_SP

0x6c - core0 pdebug status register

§core_0_iram0_exception_monitor_0: CORE_0_IRAM0_EXCEPTION_MONITOR_0

0x70 - core0 bus busy status regsiter

§core_0_iram0_exception_monitor_1: CORE_0_IRAM0_EXCEPTION_MONITOR_1

0x74 - core0 bus busy status regsiter

§core_0_dram0_exception_monitor_0: CORE_0_DRAM0_EXCEPTION_MONITOR_0

0x78 - core0 bus busy status regsiter

§core_0_dram0_exception_monitor_1: CORE_0_DRAM0_EXCEPTION_MONITOR_1

0x7c - core0 bus busy status regsiter

§core_0_dram0_exception_monitor_2: CORE_0_DRAM0_EXCEPTION_MONITOR_2

0x80 - core0 bus busy status regsiter

§core_0_dram0_exception_monitor_3: CORE_0_DRAM0_EXCEPTION_MONITOR_3

0x84 - core0 bus busy status regsiter

§core_0_dram0_exception_monitor_4: CORE_0_DRAM0_EXCEPTION_MONITOR_4

0x88 - core0 bus busy configuration regsiter

§core_0_dram0_exception_monitor_5: CORE_0_DRAM0_EXCEPTION_MONITOR_5

0x8c - core0 bus busy configuration regsiter

§core_1_montr_ena: CORE_1_MONTR_ENA

0x90 - Core1 monitor enable configuration register

§core_1_intr_raw: CORE_1_INTR_RAW

0x94 - Core1 monitor interrupt status register

§core_1_intr_ena: CORE_1_INTR_ENA

0x98 - Core1 monitor interrupt enable register

§core_1_intr_clr: CORE_1_INTR_CLR

0x9c - Core1 monitor interrupt clr register

§core_1_area_dram0_0_min: CORE_1_AREA_DRAM0_0_MIN

0xa0 - Core1 dram0 region0 addr configuration register

§core_1_area_dram0_0_max: CORE_1_AREA_DRAM0_0_MAX

0xa4 - Core1 dram0 region0 addr configuration register

§core_1_area_dram0_1_min: CORE_1_AREA_DRAM0_1_MIN

0xa8 - Core1 dram0 region1 addr configuration register

§core_1_area_dram0_1_max: CORE_1_AREA_DRAM0_1_MAX

0xac - Core1 dram0 region1 addr configuration register

§core_1_area_pif_0_min: CORE_1_AREA_PIF_0_MIN

0xb0 - Core1 PIF region0 addr configuration register

§core_1_area_pif_0_max: CORE_1_AREA_PIF_0_MAX

0xb4 - Core1 PIF region0 addr configuration register

§core_1_area_pif_1_min: CORE_1_AREA_PIF_1_MIN

0xb8 - Core1 PIF region1 addr configuration register

§core_1_area_pif_1_max: CORE_1_AREA_PIF_1_MAX

0xbc - Core1 PIF region1 addr configuration register

§core_1_area_pc: CORE_1_AREA_PC

0xc0 - Core1 area sp status register

§core_1_area_sp: CORE_1_AREA_SP

0xc4 - Core1 area pc status register

§core_1_sp_unstable: CORE_1_SP_UNSTABLE

0xc8 - Core1 sp unstable configuration register

§core_1_sp_min: CORE_1_SP_MIN

0xcc - Core1 sp region configuration regsiter

§core_1_sp_max: CORE_1_SP_MAX

0xd0 - Core1 sp region configuration regsiter

§core_1_sp_pc: CORE_1_SP_PC

0xd4 - Core1 sp pc status register

§core_1_rcd_pdebugenable: CORE_1_RCD_PDEBUGENABLE

0xd8 - Core1 pdebug configuration register

§core_1_rcd_recording: CORE_1_RCD_RECORDING

0xdc - Core1 pdebug status register

§core_1_rcd_pdebuginst: CORE_1_RCD_PDEBUGINST

0xe0 - Core1 pdebug status register

§core_1_rcd_pdebugstatus: CORE_1_RCD_PDEBUGSTATUS

0xe4 - Core1 pdebug status register

§core_1_rcd_pdebugdata: CORE_1_RCD_PDEBUGDATA

0xe8 - Core1 pdebug status register

§core_1_rcd_pdebugpc: CORE_1_RCD_PDEBUGPC

0xec - Core1 pdebug status register

§core_1_rcd_pdebugls0stat: CORE_1_RCD_PDEBUGLS0STAT

0xf0 - Core1 pdebug status register

§core_1_rcd_pdebugls0addr: CORE_1_RCD_PDEBUGLS0ADDR

0xf4 - Core1 pdebug status register

§core_1_rcd_pdebugls0data: CORE_1_RCD_PDEBUGLS0DATA

0xf8 - Core1 pdebug status register

§core_1_rcd_sp: CORE_1_RCD_SP

0xfc - Core1 pdebug status register

§core_1_iram0_exception_monitor_0: CORE_1_IRAM0_EXCEPTION_MONITOR_0

0x100 - Core1 bus busy status regsiter

§core_1_iram0_exception_monitor_1: CORE_1_IRAM0_EXCEPTION_MONITOR_1

0x104 - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_0: CORE_1_DRAM0_EXCEPTION_MONITOR_0

0x108 - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_1: CORE_1_DRAM0_EXCEPTION_MONITOR_1

0x10c - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_2: CORE_1_DRAM0_EXCEPTION_MONITOR_2

0x110 - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_3: CORE_1_DRAM0_EXCEPTION_MONITOR_3

0x114 - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_4: CORE_1_DRAM0_EXCEPTION_MONITOR_4

0x118 - Core1 bus busy status regsiter

§core_1_dram0_exception_monitor_5: CORE_1_DRAM0_EXCEPTION_MONITOR_5

0x11c - Core1 bus busy status regsiter

§core_x_iram0_dram0_exception_monitor_0: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0

0x120 - bus busy configuration register

§core_x_iram0_dram0_exception_monitor_1: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1

0x124 - bus busy configuration register

§log_setting: LOG_SETTING

0x128 - log set register

§log_data_0: LOG_DATA_0

0x12c - log check data register

§log_data_1: LOG_DATA_1

0x130 - log check data register

§log_data_2: LOG_DATA_2

0x134 - log check data register

§log_data_3: LOG_DATA_3

0x138 - log check data register

§log_data_mask: LOG_DATA_MASK

0x13c - log check data mask register

§log_min: LOG_MIN

0x140 - log check region configuration register

§log_max: LOG_MAX

0x144 - log check region configuration register

§log_mem_start: LOG_MEM_START

0x148 - log mem region configuration register

§log_mem_end: LOG_MEM_END

0x14c - log mem region configuration register

§log_mem_writing_addr: LOG_MEM_WRITING_ADDR

0x150 - log mem addr status register

§log_mem_full_flag: LOG_MEM_FULL_FLAG

0x154 - log mem status register

§date: DATE

0x1fc - version register

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