Type Alias esp32s3::lcd_cam::lcd_dly_mode::W

pub type W = W<LCD_DLY_MODE_SPEC>;

Register LCD_DLY_MODE writer

Implementations

impl W

pub fn lcd_cd_mode(&mut self) -> LCD_CD_MODE_W<'_, LCD_DLY_MODE_SPEC, 0>

Bits 0:1 - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn lcd_de_mode(&mut self) -> LCD_DE_MODE_W<'_, LCD_DLY_MODE_SPEC, 2>

Bits 2:3 - The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn lcd_hsync_mode(&mut self) -> LCD_HSYNC_MODE_W<'_, LCD_DLY_MODE_SPEC, 4>

Bits 4:5 - The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub fn lcd_vsync_mode(&mut self) -> LCD_VSYNC_MODE_W<'_, LCD_DLY_MODE_SPEC, 6>

Bits 6:7 - The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.