Struct esp32s3::sdhost::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 41 fields
    pub ctrl: CTRL,
    pub clkdiv: CLKDIV,
    pub clksrc: CLKSRC,
    pub clkena: CLKENA,
    pub tmout: TMOUT,
    pub ctype: CTYPE,
    pub blksiz: BLKSIZ,
    pub bytcnt: BYTCNT,
    pub intmask: INTMASK,
    pub cmdarg: CMDARG,
    pub cmd: CMD,
    pub resp0: RESP0,
    pub resp1: RESP1,
    pub resp2: RESP2,
    pub resp3: RESP3,
    pub mintsts: MINTSTS,
    pub rintsts: RINTSTS,
    pub status: STATUS,
    pub fifoth: FIFOTH,
    pub cdetect: CDETECT,
    pub wrtprt: WRTPRT,
    pub tcbcnt: TCBCNT,
    pub tbbcnt: TBBCNT,
    pub debnce: DEBNCE,
    pub usrid: USRID,
    pub verid: VERID,
    pub hcon: HCON,
    pub uhs: UHS,
    pub rst_n: RST_N,
    pub bmod: BMOD,
    pub pldmnd: PLDMND,
    pub dbaddr: DBADDR,
    pub idsts: IDSTS,
    pub idinten: IDINTEN,
    pub dscaddr: DSCADDR,
    pub bufaddr: BUFADDR,
    pub cardthrctl: CARDTHRCTL,
    pub emmcddr: EMMCDDR,
    pub enshift: ENSHIFT,
    pub buffifo: BUFFIFO,
    pub clk_edge_sel: CLK_EDGE_SEL,
    /* private fields */

}
Expand description

Register block

Fields§

§ctrl: CTRL

0x00 - Control register

§clkdiv: CLKDIV

0x08 - Clock divider configuration register

§clksrc: CLKSRC

0x0c - Clock source selection register

§clkena: CLKENA

0x10 - Clock enable register

§tmout: TMOUT

0x14 - Data and response timeout configuration register

§ctype: CTYPE

0x18 - Card bus width configuration register

§blksiz: BLKSIZ

0x1c - Card data block size configuration register

§bytcnt: BYTCNT

0x20 - Data transfer length configuration register

§intmask: INTMASK

0x24 - SDIO interrupt mask register

§cmdarg: CMDARG

0x28 - Command argument data register

§cmd: CMD

0x2c - Command and boot configuration register

§resp0: RESP0

0x30 - Response data register

§resp1: RESP1

0x34 - Long response data register

§resp2: RESP2

0x38 - Long response data register

§resp3: RESP3

0x3c - Long response data register

§mintsts: MINTSTS

0x40 - Masked interrupt status register

§rintsts: RINTSTS

0x44 - Raw interrupt status register

§status: STATUS

0x48 - SD/MMC status register

§fifoth: FIFOTH

0x4c - FIFO configuration register

§cdetect: CDETECT

0x50 - Card detect register

§wrtprt: WRTPRT

0x54 - Card write protection (WP) status register

§tcbcnt: TCBCNT

0x5c - Transferred byte count register

§tbbcnt: TBBCNT

0x60 - Transferred byte count register

§debnce: DEBNCE

0x64 - Debounce filter time configuration register

§usrid: USRID

0x68 - User ID (scratchpad) register

§verid: VERID

0x6c - Version ID (scratchpad) register

§hcon: HCON

0x70 - Hardware feature register

§uhs: UHS

0x74 - UHS-1 register

§rst_n: RST_N

0x78 - Card reset register

§bmod: BMOD

0x80 - Burst mode transfer configuration register

§pldmnd: PLDMND

0x84 - Poll demand configuration register

§dbaddr: DBADDR

0x88 - Descriptor base address register

§idsts: IDSTS

0x8c - IDMAC status register

§idinten: IDINTEN

0x90 - IDMAC interrupt enable register

§dscaddr: DSCADDR

0x94 - Host descriptor address pointer

§bufaddr: BUFADDR

0x98 - Host buffer address pointer register

§cardthrctl: CARDTHRCTL

0x100 - Card Threshold Control register

§emmcddr: EMMCDDR

0x10c - eMMC DDR register

§enshift: ENSHIFT

0x110 - Enable Phase Shift register

§buffifo: BUFFIFO

0x200 - CPU write and read transmit data by FIFO

§clk_edge_sel: CLK_EDGE_SEL

0x800 - SDIO control register.

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