#[repr(C)]
pub struct RegisterBlock {
Show 38 fields pub cmd: Reg<CMD_SPEC>, pub addr: Reg<ADDR_SPEC>, pub ctrl: Reg<CTRL_SPEC>, pub clock: Reg<CLOCK_SPEC>, pub user: Reg<USER_SPEC>, pub user1: Reg<USER1_SPEC>, pub user2: Reg<USER2_SPEC>, pub ms_dlen: Reg<MS_DLEN_SPEC>, pub misc: Reg<MISC_SPEC>, pub din_mode: Reg<DIN_MODE_SPEC>, pub din_num: Reg<DIN_NUM_SPEC>, pub dout_mode: Reg<DOUT_MODE_SPEC>, pub dma_conf: Reg<DMA_CONF_SPEC>, pub dma_int_ena: Reg<DMA_INT_ENA_SPEC>, pub dma_int_clr: Reg<DMA_INT_CLR_SPEC>, pub dma_int_raw: Reg<DMA_INT_RAW_SPEC>, pub dma_int_st: Reg<DMA_INT_ST_SPEC>, pub dma_int_set: Reg<DMA_INT_SET_SPEC>, pub w0: Reg<W0_SPEC>, pub w1: Reg<W1_SPEC>, pub w2: Reg<W2_SPEC>, pub w3: Reg<W3_SPEC>, pub w4: Reg<W4_SPEC>, pub w5: Reg<W5_SPEC>, pub w6: Reg<W6_SPEC>, pub w7: Reg<W7_SPEC>, pub w8: Reg<W8_SPEC>, pub w9: Reg<W9_SPEC>, pub w10: Reg<W10_SPEC>, pub w11: Reg<W11_SPEC>, pub w12: Reg<W12_SPEC>, pub w13: Reg<W13_SPEC>, pub w14: Reg<W14_SPEC>, pub w15: Reg<W15_SPEC>, pub slave: Reg<SLAVE_SPEC>, pub slave1: Reg<SLAVE1_SPEC>, pub clk_gate: Reg<CLK_GATE_SPEC>, pub date: Reg<DATE_SPEC>, /* private fields */
}
Expand description

Register block

Fields

cmd: Reg<CMD_SPEC>

0x00 - Command control register

addr: Reg<ADDR_SPEC>

0x04 - Address value register

ctrl: Reg<CTRL_SPEC>

0x08 - SPI control register

clock: Reg<CLOCK_SPEC>

0x0c - SPI clock control register

user: Reg<USER_SPEC>

0x10 - SPI USER control register

user1: Reg<USER1_SPEC>

0x14 - SPI USER control register 1

user2: Reg<USER2_SPEC>

0x18 - SPI USER control register 2

ms_dlen: Reg<MS_DLEN_SPEC>

0x1c - SPI data bit length control register

misc: Reg<MISC_SPEC>

0x20 - SPI misc register

din_mode: Reg<DIN_MODE_SPEC>

0x24 - SPI input delay mode configuration

din_num: Reg<DIN_NUM_SPEC>

0x28 - SPI input delay number configuration

dout_mode: Reg<DOUT_MODE_SPEC>

0x2c - SPI output delay mode configuration

dma_conf: Reg<DMA_CONF_SPEC>

0x30 - SPI DMA control register

dma_int_ena: Reg<DMA_INT_ENA_SPEC>

0x34 - SPI interrupt enable register

dma_int_clr: Reg<DMA_INT_CLR_SPEC>

0x38 - SPI interrupt clear register

dma_int_raw: Reg<DMA_INT_RAW_SPEC>

0x3c - SPI interrupt raw register

dma_int_st: Reg<DMA_INT_ST_SPEC>

0x40 - SPI interrupt status register

dma_int_set: Reg<DMA_INT_SET_SPEC>

0x44 - SPI interrupt software set register

w0: Reg<W0_SPEC>

0x98 - SPI CPU-controlled buffer0

w1: Reg<W1_SPEC>

0x9c - SPI CPU-controlled buffer1

w2: Reg<W2_SPEC>

0xa0 - SPI CPU-controlled buffer2

w3: Reg<W3_SPEC>

0xa4 - SPI CPU-controlled buffer3

w4: Reg<W4_SPEC>

0xa8 - SPI CPU-controlled buffer4

w5: Reg<W5_SPEC>

0xac - SPI CPU-controlled buffer5

w6: Reg<W6_SPEC>

0xb0 - SPI CPU-controlled buffer6

w7: Reg<W7_SPEC>

0xb4 - SPI CPU-controlled buffer7

w8: Reg<W8_SPEC>

0xb8 - SPI CPU-controlled buffer8

w9: Reg<W9_SPEC>

0xbc - SPI CPU-controlled buffer9

w10: Reg<W10_SPEC>

0xc0 - SPI CPU-controlled buffer10

w11: Reg<W11_SPEC>

0xc4 - SPI CPU-controlled buffer11

w12: Reg<W12_SPEC>

0xc8 - SPI CPU-controlled buffer12

w13: Reg<W13_SPEC>

0xcc - SPI CPU-controlled buffer13

w14: Reg<W14_SPEC>

0xd0 - SPI CPU-controlled buffer14

w15: Reg<W15_SPEC>

0xd4 - SPI CPU-controlled buffer15

slave: Reg<SLAVE_SPEC>

0xe0 - SPI slave control register

slave1: Reg<SLAVE1_SPEC>

0xe4 - SPI slave control register 1

clk_gate: Reg<CLK_GATE_SPEC>

0xe8 - SPI module clock and register clock control

date: Reg<DATE_SPEC>

0xf0 - Version control

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