#[repr(C)]
pub struct RegisterBlock {
Show 38 fields pub ctrl: Reg<CTRL_SPEC>, pub ctrl1: Reg<CTRL1_SPEC>, pub ctrl2: Reg<CTRL2_SPEC>, pub clock: Reg<CLOCK_SPEC>, pub user: Reg<USER_SPEC>, pub user1: Reg<USER1_SPEC>, pub user2: Reg<USER2_SPEC>, pub rd_status: Reg<RD_STATUS_SPEC>, pub ext_addr: Reg<EXT_ADDR_SPEC>, pub misc: Reg<MISC_SPEC>, pub cache_fctrl: Reg<CACHE_FCTRL_SPEC>, pub cache_sctrl: Reg<CACHE_SCTRL_SPEC>, pub sram_cmd: Reg<SRAM_CMD_SPEC>, pub sram_drd_cmd: Reg<SRAM_DRD_CMD_SPEC>, pub sram_dwr_cmd: Reg<SRAM_DWR_CMD_SPEC>, pub sram_clk: Reg<SRAM_CLK_SPEC>, pub fsm: Reg<FSM_SPEC>, pub timing_cali: Reg<TIMING_CALI_SPEC>, pub din_mode: Reg<DIN_MODE_SPEC>, pub din_num: Reg<DIN_NUM_SPEC>, pub dout_mode: Reg<DOUT_MODE_SPEC>, pub spi_smem_timing_cali: Reg<SPI_SMEM_TIMING_CALI_SPEC>, pub spi_smem_din_mode: Reg<SPI_SMEM_DIN_MODE_SPEC>, pub spi_smem_din_num: Reg<SPI_SMEM_DIN_NUM_SPEC>, pub spi_smem_dout_mode: Reg<SPI_SMEM_DOUT_MODE_SPEC>, pub ecc_ctrl: Reg<ECC_CTRL_SPEC>, pub ecc_err_addr: Reg<ECC_ERR_ADDR_SPEC>, pub ecc_err_bit: Reg<ECC_ERR_BIT_SPEC>, pub spi_smem_ac: Reg<SPI_SMEM_AC_SPEC>, pub ddr: Reg<DDR_SPEC>, pub spi_smem_ddr: Reg<SPI_SMEM_DDR_SPEC>, pub clock_gate: Reg<CLOCK_GATE_SPEC>, pub core_clk_sel: Reg<CORE_CLK_SEL_SPEC>, pub int_ena: Reg<INT_ENA_SPEC>, pub int_clr: Reg<INT_CLR_SPEC>, pub int_raw: Reg<INT_RAW_SPEC>, pub int_st: Reg<INT_ST_SPEC>, pub date: Reg<DATE_SPEC>, /* private fields */
}
Expand description

Register block

Fields

ctrl: Reg<CTRL_SPEC>

0x08 - SPI0 control register.

ctrl1: Reg<CTRL1_SPEC>

0x0c - SPI0 control 1 register.

ctrl2: Reg<CTRL2_SPEC>

0x10 - SPI0 control 2 register.

clock: Reg<CLOCK_SPEC>

0x14 - SPI_CLK clock division register when SPI0 accesses to flash.

user: Reg<USER_SPEC>

0x18 - SPI0 user register.

user1: Reg<USER1_SPEC>

0x1c - SPI0 user1 register.

user2: Reg<USER2_SPEC>

0x20 - SPI0 user2 register.

rd_status: Reg<RD_STATUS_SPEC>

0x2c - SPI0 read control register.

ext_addr: Reg<EXT_ADDR_SPEC>

0x30 - SPI0 extended address register.

misc: Reg<MISC_SPEC>

0x34 - SPI0 misc register

cache_fctrl: Reg<CACHE_FCTRL_SPEC>

0x3c - SPI0 external RAM bit mode control register.

cache_sctrl: Reg<CACHE_SCTRL_SPEC>

0x40 - SPI0 external RAM control register

sram_cmd: Reg<SRAM_CMD_SPEC>

0x44 - SPI0 external RAM mode control register

sram_drd_cmd: Reg<SRAM_DRD_CMD_SPEC>

0x48 - SPI0 external RAM DDR read command control register

sram_dwr_cmd: Reg<SRAM_DWR_CMD_SPEC>

0x4c - SPI0 external RAM DDR write command control register

sram_clk: Reg<SRAM_CLK_SPEC>

0x50 - SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

fsm: Reg<FSM_SPEC>

0x54 - SPI0 state machine(FSM) status register.

timing_cali: Reg<TIMING_CALI_SPEC>

0xa8 - SPI0 timing compensation register when accesses to flash.

din_mode: Reg<DIN_MODE_SPEC>

0xac - MSPI input timing delay mode control register when accesses to flash.

din_num: Reg<DIN_NUM_SPEC>

0xb0 - MSPI input timing delay number control register when accesses to flash.

dout_mode: Reg<DOUT_MODE_SPEC>

0xb4 - MSPI output timing delay mode control register when accesses to flash.

spi_smem_timing_cali: Reg<SPI_SMEM_TIMING_CALI_SPEC>

0xbc - SPI0 Ext_RAM timing compensation register.

spi_smem_din_mode: Reg<SPI_SMEM_DIN_MODE_SPEC>

0xc0 - MSPI input timing delay mode control register when accesses to Ext_RAM.

spi_smem_din_num: Reg<SPI_SMEM_DIN_NUM_SPEC>

0xc4 - MSPI input timing delay number control register when accesses to Ext_RAM.

spi_smem_dout_mode: Reg<SPI_SMEM_DOUT_MODE_SPEC>

0xc8 - MSPI output timing delay mode control register when accesses to Ext_RAM.

ecc_ctrl: Reg<ECC_CTRL_SPEC>

0xcc - MSPI ECC control register

ecc_err_addr: Reg<ECC_ERR_ADDR_SPEC>

0xd0 - MSPI ECC error address register

ecc_err_bit: Reg<ECC_ERR_BIT_SPEC>

0xd4 - MSPI ECC error bits register

spi_smem_ac: Reg<SPI_SMEM_AC_SPEC>

0xdc - MSPI external RAM ECC and SPI CS timing control register

ddr: Reg<DDR_SPEC>

0xe0 - SPI0 flash DDR mode control register

spi_smem_ddr: Reg<SPI_SMEM_DDR_SPEC>

0xe4 - SPI0 external RAM DDR mode control register

clock_gate: Reg<CLOCK_GATE_SPEC>

0xe8 - SPI0 clk_gate register

core_clk_sel: Reg<CORE_CLK_SEL_SPEC>

0xec - SPI0 module clock select register

int_ena: Reg<INT_ENA_SPEC>

0xf0 - SPI1 interrupt enable register

int_clr: Reg<INT_CLR_SPEC>

0xf4 - SPI1 interrupt clear register

int_raw: Reg<INT_RAW_SPEC>

0xf8 - SPI1 interrupt raw register

int_st: Reg<INT_ST_SPEC>

0xfc - SPI1 interrupt status register

date: Reg<DATE_SPEC>

0x3fc - SPI0 version control register

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