Expand description
SHA (Secure Hash Algorithm) Accelerator
Modules
Busy register.
Interrupt clear register.
Typical SHA configuration register 1.
Date register.
DMA configuration register 0.
DMA configuration register 2.
DMA configuration register 1.
Sha H memory which contains intermediate hash or finial hash.
Interrupt enable register.
Sha M memory which contains message.
Initial configuration register.
Typical SHA configuration register 0.
SHA 512/t configuration register 1.
SHA 512/t configuration register 0.
Structs
Register block
Type Definitions
BUSY register accessor: an alias for Reg<BUSY_SPEC>
CLEAR_IRQ register accessor: an alias for Reg<CLEAR_IRQ_SPEC>
CONTINUE register accessor: an alias for Reg<CONTINUE_SPEC>
DATE register accessor: an alias for Reg<DATE_SPEC>
DMA_BLOCK_NUM register accessor: an alias for Reg<DMA_BLOCK_NUM_SPEC>
DMA_CONTINUE register accessor: an alias for Reg<DMA_CONTINUE_SPEC>
DMA_START register accessor: an alias for Reg<DMA_START_SPEC>
H_MEM register accessor: an alias for Reg<H_MEM_SPEC>
IRQ_ENA register accessor: an alias for Reg<IRQ_ENA_SPEC>
MODE register accessor: an alias for Reg<MODE_SPEC>
M_MEM register accessor: an alias for Reg<M_MEM_SPEC>
START register accessor: an alias for Reg<START_SPEC>
T_LENGTH register accessor: an alias for Reg<T_LENGTH_SPEC>
T_STRING register accessor: an alias for Reg<T_STRING_SPEC>