Struct esp32s3::sensitive::RegisterBlock

source · [−]
#[repr(C)]
pub struct RegisterBlock {
Show 197 fields
    pub cache_dataarray_connect_0: Reg<CACHE_DATAARRAY_CONNECT_0_SPEC>,
    pub cache_dataarray_connect_1: Reg<CACHE_DATAARRAY_CONNECT_1_SPEC>,
    pub apb_peripheral_access_0: Reg<APB_PERIPHERAL_ACCESS_0_SPEC>,
    pub apb_peripheral_access_1: Reg<APB_PERIPHERAL_ACCESS_1_SPEC>,
    pub internal_sram_usage_0: Reg<INTERNAL_SRAM_USAGE_0_SPEC>,
    pub internal_sram_usage_1: Reg<INTERNAL_SRAM_USAGE_1_SPEC>,
    pub internal_sram_usage_2: Reg<INTERNAL_SRAM_USAGE_2_SPEC>,
    pub internal_sram_usage_3: Reg<INTERNAL_SRAM_USAGE_3_SPEC>,
    pub internal_sram_usage_4: Reg<INTERNAL_SRAM_USAGE_4_SPEC>,
    pub retention_disable: Reg<RETENTION_DISABLE_SPEC>,
    pub cache_tag_access_0: Reg<CACHE_TAG_ACCESS_0_SPEC>,
    pub cache_tag_access_1: Reg<CACHE_TAG_ACCESS_1_SPEC>,
    pub cache_mmu_access_0: Reg<CACHE_MMU_ACCESS_0_SPEC>,
    pub cache_mmu_access_1: Reg<CACHE_MMU_ACCESS_1_SPEC>,
    pub dma_apbperi_spi2_pms_constrain_0: Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_spi2_pms_constrain_1: Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_spi3_pms_constrain_0: Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_spi3_pms_constrain_1: Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_uhci0_pms_constrain_0: Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_uhci0_pms_constrain_1: Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_i2s0_pms_constrain_0: Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_i2s0_pms_constrain_1: Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_i2s1_pms_constrain_0: Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_i2s1_pms_constrain_1: Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_mac_pms_constrain_0: Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_mac_pms_constrain_1: Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_backup_pms_constrain_0: Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_backup_pms_constrain_1: Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_aes_pms_constrain_0: Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_aes_pms_constrain_1: Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_sha_pms_constrain_0: Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_sha_pms_constrain_1: Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_adc_dac_pms_constrain_0: Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_adc_dac_pms_constrain_1: Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_rmt_pms_constrain_0: Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_rmt_pms_constrain_1: Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_lcd_cam_pms_constrain_0: Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_lcd_cam_pms_constrain_1: Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_usb_pms_constrain_0: Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_usb_pms_constrain_1: Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_lc_pms_constrain_0: Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_lc_pms_constrain_1: Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_sdio_pms_constrain_0: Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_SPEC>,
    pub dma_apbperi_sdio_pms_constrain_1: Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC>,
    pub dma_apbperi_pms_monitor_0: Reg<DMA_APBPERI_PMS_MONITOR_0_SPEC>,
    pub dma_apbperi_pms_monitor_1: Reg<DMA_APBPERI_PMS_MONITOR_1_SPEC>,
    pub dma_apbperi_pms_monitor_2: Reg<DMA_APBPERI_PMS_MONITOR_2_SPEC>,
    pub dma_apbperi_pms_monitor_3: Reg<DMA_APBPERI_PMS_MONITOR_3_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_0: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_1: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_2: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_3: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_4: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>,
    pub core_x_iram0_dram0_dma_split_line_constrain_5: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>,
    pub core_x_iram0_pms_constrain_0: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_0_SPEC>,
    pub core_x_iram0_pms_constrain_1: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC>,
    pub core_x_iram0_pms_constrain_2: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC>,
    pub core_0_iram0_pms_monitor_0: Reg<CORE_0_IRAM0_PMS_MONITOR_0_SPEC>,
    pub core_0_iram0_pms_monitor_1: Reg<CORE_0_IRAM0_PMS_MONITOR_1_SPEC>,
    pub core_0_iram0_pms_monitor_2: Reg<CORE_0_IRAM0_PMS_MONITOR_2_SPEC>,
    pub core_1_iram0_pms_monitor_0: Reg<CORE_1_IRAM0_PMS_MONITOR_0_SPEC>,
    pub core_1_iram0_pms_monitor_1: Reg<CORE_1_IRAM0_PMS_MONITOR_1_SPEC>,
    pub core_1_iram0_pms_monitor_2: Reg<CORE_1_IRAM0_PMS_MONITOR_2_SPEC>,
    pub core_x_dram0_pms_constrain_0: Reg<CORE_X_DRAM0_PMS_CONSTRAIN_0_SPEC>,
    pub core_x_dram0_pms_constrain_1: Reg<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC>,
    pub core_0_dram0_pms_monitor_0: Reg<CORE_0_DRAM0_PMS_MONITOR_0_SPEC>,
    pub core_0_dram0_pms_monitor_1: Reg<CORE_0_DRAM0_PMS_MONITOR_1_SPEC>,
    pub core_0_dram0_pms_monitor_2: Reg<CORE_0_DRAM0_PMS_MONITOR_2_SPEC>,
    pub core_0_dram0_pms_monitor_3: Reg<CORE_0_DRAM0_PMS_MONITOR_3_SPEC>,
    pub core_1_dram0_pms_monitor_0: Reg<CORE_1_DRAM0_PMS_MONITOR_0_SPEC>,
    pub core_1_dram0_pms_monitor_1: Reg<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>,
    pub core_1_dram0_pms_monitor_2: Reg<CORE_1_DRAM0_PMS_MONITOR_2_SPEC>,
    pub core_1_dram0_pms_monitor_3: Reg<CORE_1_DRAM0_PMS_MONITOR_3_SPEC>,
    pub core_0_pif_pms_constrain_0: Reg<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC>,
    pub core_0_pif_pms_constrain_1: Reg<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>,
    pub core_0_pif_pms_constrain_2: Reg<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC>,
    pub core_0_pif_pms_constrain_3: Reg<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC>,
    pub core_0_pif_pms_constrain_4: Reg<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC>,
    pub core_0_pif_pms_constrain_5: Reg<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC>,
    pub core_0_pif_pms_constrain_6: Reg<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC>,
    pub core_0_pif_pms_constrain_7: Reg<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>,
    pub core_0_pif_pms_constrain_8: Reg<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>,
    pub core_0_pif_pms_constrain_9: Reg<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>,
    pub core_0_pif_pms_constrain_10: Reg<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC>,
    pub core_0_pif_pms_constrain_11: Reg<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>,
    pub core_0_pif_pms_constrain_12: Reg<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC>,
    pub core_0_pif_pms_constrain_13: Reg<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>,
    pub core_0_pif_pms_constrain_14: Reg<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC>,
    pub core_0_region_pms_constrain_0: Reg<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC>,
    pub core_0_region_pms_constrain_1: Reg<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC>,
    pub core_0_region_pms_constrain_2: Reg<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC>,
    pub core_0_region_pms_constrain_3: Reg<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC>,
    pub core_0_region_pms_constrain_4: Reg<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC>,
    pub core_0_region_pms_constrain_5: Reg<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC>,
    pub core_0_region_pms_constrain_6: Reg<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC>,
    pub core_0_region_pms_constrain_7: Reg<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC>,
    pub core_0_region_pms_constrain_8: Reg<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC>,
    pub core_0_region_pms_constrain_9: Reg<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC>,
    pub core_0_region_pms_constrain_10: Reg<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC>,
    pub core_0_region_pms_constrain_11: Reg<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC>,
    pub core_0_region_pms_constrain_12: Reg<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC>,
    pub core_0_region_pms_constrain_13: Reg<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC>,
    pub core_0_region_pms_constrain_14: Reg<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC>,
    pub core_0_pif_pms_monitor_0: Reg<CORE_0_PIF_PMS_MONITOR_0_SPEC>,
    pub core_0_pif_pms_monitor_1: Reg<CORE_0_PIF_PMS_MONITOR_1_SPEC>,
    pub core_0_pif_pms_monitor_2: Reg<CORE_0_PIF_PMS_MONITOR_2_SPEC>,
    pub core_0_pif_pms_monitor_3: Reg<CORE_0_PIF_PMS_MONITOR_3_SPEC>,
    pub core_0_pif_pms_monitor_4: Reg<CORE_0_PIF_PMS_MONITOR_4_SPEC>,
    pub core_0_pif_pms_monitor_5: Reg<CORE_0_PIF_PMS_MONITOR_5_SPEC>,
    pub core_0_pif_pms_monitor_6: Reg<CORE_0_PIF_PMS_MONITOR_6_SPEC>,
    pub core_0_vecbase_override_lock: Reg<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC>,
    pub core_0_vecbase_override_0: Reg<CORE_0_VECBASE_OVERRIDE_0_SPEC>,
    pub core_0_vecbase_override_1: Reg<CORE_0_VECBASE_OVERRIDE_1_SPEC>,
    pub core_0_vecbase_override_2: Reg<CORE_0_VECBASE_OVERRIDE_2_SPEC>,
    pub core_0_toomanyexceptions_m_override_0: Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>,
    pub core_0_toomanyexceptions_m_override_1: Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>,
    pub core_1_pif_pms_constrain_0: Reg<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC>,
    pub core_1_pif_pms_constrain_1: Reg<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC>,
    pub core_1_pif_pms_constrain_2: Reg<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC>,
    pub core_1_pif_pms_constrain_3: Reg<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC>,
    pub core_1_pif_pms_constrain_4: Reg<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC>,
    pub core_1_pif_pms_constrain_5: Reg<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>,
    pub core_1_pif_pms_constrain_6: Reg<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC>,
    pub core_1_pif_pms_constrain_7: Reg<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC>,
    pub core_1_pif_pms_constrain_8: Reg<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC>,
    pub core_1_pif_pms_constrain_9: Reg<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC>,
    pub core_1_pif_pms_constrain_10: Reg<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC>,
    pub core_1_pif_pms_constrain_11: Reg<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>,
    pub core_1_pif_pms_constrain_12: Reg<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC>,
    pub core_1_pif_pms_constrain_13: Reg<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>,
    pub core_1_pif_pms_constrain_14: Reg<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC>,
    pub core_1_region_pms_constrain_0: Reg<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC>,
    pub core_1_region_pms_constrain_1: Reg<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC>,
    pub core_1_region_pms_constrain_2: Reg<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC>,
    pub core_1_region_pms_constrain_3: Reg<CORE_1_REGION_PMS_CONSTRAIN_3_SPEC>,
    pub core_1_region_pms_constrain_4: Reg<CORE_1_REGION_PMS_CONSTRAIN_4_SPEC>,
    pub core_1_region_pms_constrain_5: Reg<CORE_1_REGION_PMS_CONSTRAIN_5_SPEC>,
    pub core_1_region_pms_constrain_6: Reg<CORE_1_REGION_PMS_CONSTRAIN_6_SPEC>,
    pub core_1_region_pms_constrain_7: Reg<CORE_1_REGION_PMS_CONSTRAIN_7_SPEC>,
    pub core_1_region_pms_constrain_8: Reg<CORE_1_REGION_PMS_CONSTRAIN_8_SPEC>,
    pub core_1_region_pms_constrain_9: Reg<CORE_1_REGION_PMS_CONSTRAIN_9_SPEC>,
    pub core_1_region_pms_constrain_10: Reg<CORE_1_REGION_PMS_CONSTRAIN_10_SPEC>,
    pub core_1_region_pms_constrain_11: Reg<CORE_1_REGION_PMS_CONSTRAIN_11_SPEC>,
    pub core_1_region_pms_constrain_12: Reg<CORE_1_REGION_PMS_CONSTRAIN_12_SPEC>,
    pub core_1_region_pms_constrain_13: Reg<CORE_1_REGION_PMS_CONSTRAIN_13_SPEC>,
    pub core_1_region_pms_constrain_14: Reg<CORE_1_REGION_PMS_CONSTRAIN_14_SPEC>,
    pub core_1_pif_pms_monitor_0: Reg<CORE_1_PIF_PMS_MONITOR_0_SPEC>,
    pub core_1_pif_pms_monitor_1: Reg<CORE_1_PIF_PMS_MONITOR_1_SPEC>,
    pub core_1_pif_pms_monitor_2: Reg<CORE_1_PIF_PMS_MONITOR_2_SPEC>,
    pub core_1_pif_pms_monitor_3: Reg<CORE_1_PIF_PMS_MONITOR_3_SPEC>,
    pub core_1_pif_pms_monitor_4: Reg<CORE_1_PIF_PMS_MONITOR_4_SPEC>,
    pub core_1_pif_pms_monitor_5: Reg<CORE_1_PIF_PMS_MONITOR_5_SPEC>,
    pub core_1_pif_pms_monitor_6: Reg<CORE_1_PIF_PMS_MONITOR_6_SPEC>,
    pub core_1_vecbase_override_lock: Reg<CORE_1_VECBASE_OVERRIDE_LOCK_SPEC>,
    pub core_1_vecbase_override_0: Reg<CORE_1_VECBASE_OVERRIDE_0_SPEC>,
    pub core_1_vecbase_override_1: Reg<CORE_1_VECBASE_OVERRIDE_1_SPEC>,
    pub core_1_vecbase_override_2: Reg<CORE_1_VECBASE_OVERRIDE_2_SPEC>,
    pub core_1_toomanyexceptions_m_override_0: Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>,
    pub core_1_toomanyexceptions_m_override_1: Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>,
    pub backup_bus_pms_constrain_0: Reg<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC>,
    pub backup_bus_pms_constrain_1: Reg<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC>,
    pub backup_bus_pms_constrain_2: Reg<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC>,
    pub backup_bus_pms_constrain_3: Reg<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC>,
    pub backup_bus_pms_constrain_4: Reg<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC>,
    pub backup_bus_pms_constrain_5: Reg<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC>,
    pub backup_bus_pms_constrain_6: Reg<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC>,
    pub backup_bus_pms_monitor_0: Reg<BACKUP_BUS_PMS_MONITOR_0_SPEC>,
    pub backup_bus_pms_monitor_1: Reg<BACKUP_BUS_PMS_MONITOR_1_SPEC>,
    pub backup_bus_pms_monitor_2: Reg<BACKUP_BUS_PMS_MONITOR_2_SPEC>,
    pub backup_bus_pms_monitor_3: Reg<BACKUP_BUS_PMS_MONITOR_3_SPEC>,
    pub edma_boundary_lock: Reg<EDMA_BOUNDARY_LOCK_SPEC>,
    pub edma_boundary_0: Reg<EDMA_BOUNDARY_0_SPEC>,
    pub edma_boundary_1: Reg<EDMA_BOUNDARY_1_SPEC>,
    pub edma_boundary_2: Reg<EDMA_BOUNDARY_2_SPEC>,
    pub edma_pms_spi2_lock: Reg<EDMA_PMS_SPI2_LOCK_SPEC>,
    pub edma_pms_spi2: Reg<EDMA_PMS_SPI2_SPEC>,
    pub edma_pms_spi3_lock: Reg<EDMA_PMS_SPI3_LOCK_SPEC>,
    pub edma_pms_spi3: Reg<EDMA_PMS_SPI3_SPEC>,
    pub edma_pms_uhci0_lock: Reg<EDMA_PMS_UHCI0_LOCK_SPEC>,
    pub edma_pms_uhci0: Reg<EDMA_PMS_UHCI0_SPEC>,
    pub edma_pms_i2s0_lock: Reg<EDMA_PMS_I2S0_LOCK_SPEC>,
    pub edma_pms_i2s0: Reg<EDMA_PMS_I2S0_SPEC>,
    pub edma_pms_i2s1_lock: Reg<EDMA_PMS_I2S1_LOCK_SPEC>,
    pub edma_pms_i2s1: Reg<EDMA_PMS_I2S1_SPEC>,
    pub edma_pms_lcd_cam_lock: Reg<EDMA_PMS_LCD_CAM_LOCK_SPEC>,
    pub edma_pms_lcd_cam: Reg<EDMA_PMS_LCD_CAM_SPEC>,
    pub edma_pms_aes_lock: Reg<EDMA_PMS_AES_LOCK_SPEC>,
    pub edma_pms_aes: Reg<EDMA_PMS_AES_SPEC>,
    pub edma_pms_sha_lock: Reg<EDMA_PMS_SHA_LOCK_SPEC>,
    pub edma_pms_sha: Reg<EDMA_PMS_SHA_SPEC>,
    pub edma_pms_adc_dac_lock: Reg<EDMA_PMS_ADC_DAC_LOCK_SPEC>,
    pub edma_pms_adc_dac: Reg<EDMA_PMS_ADC_DAC_SPEC>,
    pub edma_pms_rmt_lock: Reg<EDMA_PMS_RMT_LOCK_SPEC>,
    pub edma_pms_rmt: Reg<EDMA_PMS_RMT_SPEC>,
    pub clock_gate_reg: Reg<CLOCK_GATE_REG_SPEC>,
    pub rtc_pms: Reg<RTC_PMS_SPEC>,
    pub date: Reg<DATE_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields

cache_dataarray_connect_0: Reg<CACHE_DATAARRAY_CONNECT_0_SPEC>

0x00 - Cache data array configuration register 0.

cache_dataarray_connect_1: Reg<CACHE_DATAARRAY_CONNECT_1_SPEC>

0x04 - Cache data array configuration register 1.

apb_peripheral_access_0: Reg<APB_PERIPHERAL_ACCESS_0_SPEC>

0x08 - APB peripheral configuration register 0.

apb_peripheral_access_1: Reg<APB_PERIPHERAL_ACCESS_1_SPEC>

0x0c - APB peripheral configuration register 1.

internal_sram_usage_0: Reg<INTERNAL_SRAM_USAGE_0_SPEC>

0x10 - Internal SRAM configuration register 0.

internal_sram_usage_1: Reg<INTERNAL_SRAM_USAGE_1_SPEC>

0x14 - Internal SRAM configuration register 1.

internal_sram_usage_2: Reg<INTERNAL_SRAM_USAGE_2_SPEC>

0x18 - Internal SRAM configuration register 2.

internal_sram_usage_3: Reg<INTERNAL_SRAM_USAGE_3_SPEC>

0x1c - Internal SRAM configuration register 3.

internal_sram_usage_4: Reg<INTERNAL_SRAM_USAGE_4_SPEC>

0x20 - Internal SRAM configuration register 4.

retention_disable: Reg<RETENTION_DISABLE_SPEC>

0x24 - Retention configuration register.

cache_tag_access_0: Reg<CACHE_TAG_ACCESS_0_SPEC>

0x28 - Cache tag configuration register 0.

cache_tag_access_1: Reg<CACHE_TAG_ACCESS_1_SPEC>

0x2c - Cache tag configuration register 1.

cache_mmu_access_0: Reg<CACHE_MMU_ACCESS_0_SPEC>

0x30 - Cache MMU configuration register 0.

cache_mmu_access_1: Reg<CACHE_MMU_ACCESS_1_SPEC>

0x34 - Cache MMU configuration register 1.

dma_apbperi_spi2_pms_constrain_0: Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_SPEC>

0x38 - spi2 dma permission configuration register 0.

dma_apbperi_spi2_pms_constrain_1: Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC>

0x3c - spi2 dma permission configuration register 1.

dma_apbperi_spi3_pms_constrain_0: Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_SPEC>

0x40 - spi3 dma permission configuration register 0.

dma_apbperi_spi3_pms_constrain_1: Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC>

0x44 - spi3 dma permission configuration register 1.

dma_apbperi_uhci0_pms_constrain_0: Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_SPEC>

0x48 - uhci0 dma permission configuration register 0.

dma_apbperi_uhci0_pms_constrain_1: Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC>

0x4c - uhci0 dma permission configuration register 1.

dma_apbperi_i2s0_pms_constrain_0: Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_SPEC>

0x50 - i2s0 dma permission configuration register 0.

dma_apbperi_i2s0_pms_constrain_1: Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC>

0x54 - i2s0 dma permission configuration register 1.

dma_apbperi_i2s1_pms_constrain_0: Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_SPEC>

0x58 - i2s1 dma permission configuration register 0.

dma_apbperi_i2s1_pms_constrain_1: Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC>

0x5c - i2s1 dma permission configuration register 1.

dma_apbperi_mac_pms_constrain_0: Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_0_SPEC>

0x60 - mac dma permission configuration register 0.

dma_apbperi_mac_pms_constrain_1: Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC>

0x64 - mac dma permission configuration register 1.

dma_apbperi_backup_pms_constrain_0: Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_SPEC>

0x68 - backup dma permission configuration register 0.

dma_apbperi_backup_pms_constrain_1: Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC>

0x6c - backup dma permission configuration register 1.

dma_apbperi_aes_pms_constrain_0: Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_0_SPEC>

0x70 - aes dma permission configuration register 0.

dma_apbperi_aes_pms_constrain_1: Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC>

0x74 - aes dma permission configuration register 1.

dma_apbperi_sha_pms_constrain_0: Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_0_SPEC>

0x78 - sha dma permission configuration register 0.

dma_apbperi_sha_pms_constrain_1: Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC>

0x7c - sha dma permission configuration register 1.

dma_apbperi_adc_dac_pms_constrain_0: Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_SPEC>

0x80 - adc_dac dma permission configuration register 0.

dma_apbperi_adc_dac_pms_constrain_1: Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC>

0x84 - adc_dac dma permission configuration register 1.

dma_apbperi_rmt_pms_constrain_0: Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_0_SPEC>

0x88 - rmt dma permission configuration register 0.

dma_apbperi_rmt_pms_constrain_1: Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC>

0x8c - rmt dma permission configuration register 1.

dma_apbperi_lcd_cam_pms_constrain_0: Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_SPEC>

0x90 - lcd_cam dma permission configuration register 0.

dma_apbperi_lcd_cam_pms_constrain_1: Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC>

0x94 - lcd_cam dma permission configuration register 1.

dma_apbperi_usb_pms_constrain_0: Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_0_SPEC>

0x98 - usb dma permission configuration register 0.

dma_apbperi_usb_pms_constrain_1: Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC>

0x9c - usb dma permission configuration register 1.

dma_apbperi_lc_pms_constrain_0: Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_0_SPEC>

0xa0 - lc dma permission configuration register 0.

dma_apbperi_lc_pms_constrain_1: Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC>

0xa4 - lc dma permission configuration register 1.

dma_apbperi_sdio_pms_constrain_0: Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_SPEC>

0xa8 - sdio dma permission configuration register 0.

dma_apbperi_sdio_pms_constrain_1: Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC>

0xac - sdio dma permission configuration register 1.

dma_apbperi_pms_monitor_0: Reg<DMA_APBPERI_PMS_MONITOR_0_SPEC>

0xb0 - dma permission monitor configuration register 0.

dma_apbperi_pms_monitor_1: Reg<DMA_APBPERI_PMS_MONITOR_1_SPEC>

0xb4 - dma permission monitor configuration register 1.

dma_apbperi_pms_monitor_2: Reg<DMA_APBPERI_PMS_MONITOR_2_SPEC>

0xb8 - dma permission monitor configuration register 2.

dma_apbperi_pms_monitor_3: Reg<DMA_APBPERI_PMS_MONITOR_3_SPEC>

0xbc - dma permission monitor configuration register 3.

core_x_iram0_dram0_dma_split_line_constrain_0: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_SPEC>

0xc0 - sram split line configuration register 0

core_x_iram0_dram0_dma_split_line_constrain_1: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC>

0xc4 - sram split line configuration register 1

core_x_iram0_dram0_dma_split_line_constrain_2: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC>

0xc8 - sram split line configuration register 1

core_x_iram0_dram0_dma_split_line_constrain_3: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC>

0xcc - sram split line configuration register 1

core_x_iram0_dram0_dma_split_line_constrain_4: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC>

0xd0 - sram split line configuration register 1

core_x_iram0_dram0_dma_split_line_constrain_5: Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC>

0xd4 - sram split line configuration register 1

core_x_iram0_pms_constrain_0: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_0_SPEC>

0xd8 - corex iram0 permission configuration register 0

core_x_iram0_pms_constrain_1: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC>

0xdc - corex iram0 permission configuration register 0

core_x_iram0_pms_constrain_2: Reg<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC>

0xe0 - corex iram0 permission configuration register 1

core_0_iram0_pms_monitor_0: Reg<CORE_0_IRAM0_PMS_MONITOR_0_SPEC>

0xe4 - core0 iram0 permission monitor configuration register 0

core_0_iram0_pms_monitor_1: Reg<CORE_0_IRAM0_PMS_MONITOR_1_SPEC>

0xe8 - core0 iram0 permission monitor configuration register 1

core_0_iram0_pms_monitor_2: Reg<CORE_0_IRAM0_PMS_MONITOR_2_SPEC>

0xec - core0 iram0 permission monitor configuration register 2

core_1_iram0_pms_monitor_0: Reg<CORE_1_IRAM0_PMS_MONITOR_0_SPEC>

0xf0 - core1 iram0 permission monitor configuration register 0

core_1_iram0_pms_monitor_1: Reg<CORE_1_IRAM0_PMS_MONITOR_1_SPEC>

0xf4 - core1 iram0 permission monitor configuration register 1

core_1_iram0_pms_monitor_2: Reg<CORE_1_IRAM0_PMS_MONITOR_2_SPEC>

0xf8 - core1 iram0 permission monitor configuration register 2

core_x_dram0_pms_constrain_0: Reg<CORE_X_DRAM0_PMS_CONSTRAIN_0_SPEC>

0xfc - corex dram0 permission configuration register 0

core_x_dram0_pms_constrain_1: Reg<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC>

0x100 - corex dram0 permission configuration register 1

core_0_dram0_pms_monitor_0: Reg<CORE_0_DRAM0_PMS_MONITOR_0_SPEC>

0x104 - core0 dram0 permission monitor configuration register 0

core_0_dram0_pms_monitor_1: Reg<CORE_0_DRAM0_PMS_MONITOR_1_SPEC>

0x108 - core0 dram0 permission monitor configuration register 1

core_0_dram0_pms_monitor_2: Reg<CORE_0_DRAM0_PMS_MONITOR_2_SPEC>

0x10c - core0 dram0 permission monitor configuration register 2.

core_0_dram0_pms_monitor_3: Reg<CORE_0_DRAM0_PMS_MONITOR_3_SPEC>

0x110 - core0 dram0 permission monitor configuration register 3.

core_1_dram0_pms_monitor_0: Reg<CORE_1_DRAM0_PMS_MONITOR_0_SPEC>

0x114 - core1 dram0 permission monitor configuration register 0

core_1_dram0_pms_monitor_1: Reg<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>

0x118 - core1 dram0 permission monitor configuration register 1

core_1_dram0_pms_monitor_2: Reg<CORE_1_DRAM0_PMS_MONITOR_2_SPEC>

0x11c - core1 dram0 permission monitor configuration register 2.

core_1_dram0_pms_monitor_3: Reg<CORE_1_DRAM0_PMS_MONITOR_3_SPEC>

0x120 - core1 dram0 permission monitor configuration register 3.

core_0_pif_pms_constrain_0: Reg<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC>

0x124 - Core0 access peripherals permission configuration register 0.

core_0_pif_pms_constrain_1: Reg<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>

0x128 - Core0 access peripherals permission configuration register 1.

core_0_pif_pms_constrain_2: Reg<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC>

0x12c - Core0 access peripherals permission configuration register 2.

core_0_pif_pms_constrain_3: Reg<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC>

0x130 - Core0 access peripherals permission configuration register 3.

core_0_pif_pms_constrain_4: Reg<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC>

0x134 - Core0 access peripherals permission configuration register 4.

core_0_pif_pms_constrain_5: Reg<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC>

0x138 - Core0 access peripherals permission configuration register 5.

core_0_pif_pms_constrain_6: Reg<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC>

0x13c - Core0 access peripherals permission configuration register 6.

core_0_pif_pms_constrain_7: Reg<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>

0x140 - Core0 access peripherals permission configuration register 7.

core_0_pif_pms_constrain_8: Reg<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>

0x144 - Core0 access peripherals permission configuration register 8.

core_0_pif_pms_constrain_9: Reg<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>

0x148 - Core0 access peripherals permission configuration register 9.

core_0_pif_pms_constrain_10: Reg<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC>

0x14c - Core0 access peripherals permission configuration register 10.

core_0_pif_pms_constrain_11: Reg<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>

0x150 - Core0 access peripherals permission configuration register 11.

core_0_pif_pms_constrain_12: Reg<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC>

0x154 - Core0 access peripherals permission configuration register 12.

core_0_pif_pms_constrain_13: Reg<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>

0x158 - Core0 access peripherals permission configuration register 13.

core_0_pif_pms_constrain_14: Reg<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC>

0x15c - Core0 access peripherals permission configuration register 14.

core_0_region_pms_constrain_0: Reg<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC>

0x160 - Core0 region permission register 0.

core_0_region_pms_constrain_1: Reg<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC>

0x164 - Core0 region permission register 1.

core_0_region_pms_constrain_2: Reg<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC>

0x168 - Core0 region permission register 2.

core_0_region_pms_constrain_3: Reg<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC>

0x16c - Core0 region permission register 3.

core_0_region_pms_constrain_4: Reg<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC>

0x170 - Core0 region permission register 4.

core_0_region_pms_constrain_5: Reg<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC>

0x174 - Core0 region permission register 5.

core_0_region_pms_constrain_6: Reg<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC>

0x178 - Core0 region permission register 6.

core_0_region_pms_constrain_7: Reg<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC>

0x17c - Core0 region permission register 7.

core_0_region_pms_constrain_8: Reg<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC>

0x180 - Core0 region permission register 8.

core_0_region_pms_constrain_9: Reg<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC>

0x184 - Core0 region permission register 9.

core_0_region_pms_constrain_10: Reg<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC>

0x188 - Core0 region permission register 10.

core_0_region_pms_constrain_11: Reg<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC>

0x18c - Core0 region permission register 11.

core_0_region_pms_constrain_12: Reg<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC>

0x190 - Core0 region permission register 12.

core_0_region_pms_constrain_13: Reg<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC>

0x194 - Core0 region permission register 13.

core_0_region_pms_constrain_14: Reg<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC>

0x198 - Core0 region permission register 14.

core_0_pif_pms_monitor_0: Reg<CORE_0_PIF_PMS_MONITOR_0_SPEC>

0x19c - Core0 permission report register 0.

core_0_pif_pms_monitor_1: Reg<CORE_0_PIF_PMS_MONITOR_1_SPEC>

0x1a0 - Core0 permission report register 1.

core_0_pif_pms_monitor_2: Reg<CORE_0_PIF_PMS_MONITOR_2_SPEC>

0x1a4 - Core0 permission report register 2.

core_0_pif_pms_monitor_3: Reg<CORE_0_PIF_PMS_MONITOR_3_SPEC>

0x1a8 - Core0 permission report register 3.

core_0_pif_pms_monitor_4: Reg<CORE_0_PIF_PMS_MONITOR_4_SPEC>

0x1ac - Core0 permission report register 4.

core_0_pif_pms_monitor_5: Reg<CORE_0_PIF_PMS_MONITOR_5_SPEC>

0x1b0 - Core0 permission report register 5.

core_0_pif_pms_monitor_6: Reg<CORE_0_PIF_PMS_MONITOR_6_SPEC>

0x1b4 - Core0 permission report register 6.

core_0_vecbase_override_lock: Reg<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC>

0x1b8 - core0 vecbase override configuration register 0

core_0_vecbase_override_0: Reg<CORE_0_VECBASE_OVERRIDE_0_SPEC>

0x1bc - core0 vecbase override configuration register 0

core_0_vecbase_override_1: Reg<CORE_0_VECBASE_OVERRIDE_1_SPEC>

0x1c0 - core0 vecbase override configuration register 1

core_0_vecbase_override_2: Reg<CORE_0_VECBASE_OVERRIDE_2_SPEC>

0x1c4 - core0 vecbase override configuration register 1

core_0_toomanyexceptions_m_override_0: Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>

0x1c8 - core0 toomanyexception override configuration register 0.

core_0_toomanyexceptions_m_override_1: Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>

0x1cc - core0 toomanyexception override configuration register 1.

core_1_pif_pms_constrain_0: Reg<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC>

0x1d0 - Core1 access peripherals permission configuration register 0.

core_1_pif_pms_constrain_1: Reg<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC>

0x1d4 - Core1 access peripherals permission configuration register 1.

core_1_pif_pms_constrain_2: Reg<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC>

0x1d8 - Core1 access peripherals permission configuration register 2.

core_1_pif_pms_constrain_3: Reg<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC>

0x1dc - Core1 access peripherals permission configuration register 3.

core_1_pif_pms_constrain_4: Reg<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC>

0x1e0 - Core1 access peripherals permission configuration register 4.

core_1_pif_pms_constrain_5: Reg<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>

0x1e4 - Core1 access peripherals permission configuration register 5.

core_1_pif_pms_constrain_6: Reg<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC>

0x1e8 - Core1 access peripherals permission configuration register 6.

core_1_pif_pms_constrain_7: Reg<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC>

0x1ec - Core1 access peripherals permission configuration register 7.

core_1_pif_pms_constrain_8: Reg<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC>

0x1f0 - Core1 access peripherals permission configuration register 8.

core_1_pif_pms_constrain_9: Reg<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC>

0x1f4 - Core1 access peripherals permission configuration register 9.

core_1_pif_pms_constrain_10: Reg<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC>

0x1f8 - core1 access peripherals permission configuration register 10.

core_1_pif_pms_constrain_11: Reg<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>

0x1fc - core1 access peripherals permission configuration register 11.

core_1_pif_pms_constrain_12: Reg<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC>

0x200 - core1 access peripherals permission configuration register 12.

core_1_pif_pms_constrain_13: Reg<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>

0x204 - core1 access peripherals permission configuration register 13.

core_1_pif_pms_constrain_14: Reg<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC>

0x208 - core1 access peripherals permission configuration register 14.

core_1_region_pms_constrain_0: Reg<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC>

0x20c - core1 region permission register 0.

core_1_region_pms_constrain_1: Reg<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC>

0x210 - core1 region permission register 1.

core_1_region_pms_constrain_2: Reg<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC>

0x214 - core1 region permission register 2.

core_1_region_pms_constrain_3: Reg<CORE_1_REGION_PMS_CONSTRAIN_3_SPEC>

0x218 - core1 region permission register 3.

core_1_region_pms_constrain_4: Reg<CORE_1_REGION_PMS_CONSTRAIN_4_SPEC>

0x21c - core1 region permission register 4.

core_1_region_pms_constrain_5: Reg<CORE_1_REGION_PMS_CONSTRAIN_5_SPEC>

0x220 - core1 region permission register 5.

core_1_region_pms_constrain_6: Reg<CORE_1_REGION_PMS_CONSTRAIN_6_SPEC>

0x224 - core1 region permission register 6.

core_1_region_pms_constrain_7: Reg<CORE_1_REGION_PMS_CONSTRAIN_7_SPEC>

0x228 - core1 region permission register 7.

core_1_region_pms_constrain_8: Reg<CORE_1_REGION_PMS_CONSTRAIN_8_SPEC>

0x22c - core1 region permission register 8.

core_1_region_pms_constrain_9: Reg<CORE_1_REGION_PMS_CONSTRAIN_9_SPEC>

0x230 - core1 region permission register 9.

core_1_region_pms_constrain_10: Reg<CORE_1_REGION_PMS_CONSTRAIN_10_SPEC>

0x234 - core1 region permission register 10.

core_1_region_pms_constrain_11: Reg<CORE_1_REGION_PMS_CONSTRAIN_11_SPEC>

0x238 - core1 region permission register 11.

core_1_region_pms_constrain_12: Reg<CORE_1_REGION_PMS_CONSTRAIN_12_SPEC>

0x23c - core1 region permission register 12.

core_1_region_pms_constrain_13: Reg<CORE_1_REGION_PMS_CONSTRAIN_13_SPEC>

0x240 - core1 region permission register 13.

core_1_region_pms_constrain_14: Reg<CORE_1_REGION_PMS_CONSTRAIN_14_SPEC>

0x244 - core1 region permission register 14.

core_1_pif_pms_monitor_0: Reg<CORE_1_PIF_PMS_MONITOR_0_SPEC>

0x248 - core1 permission report register 0.

core_1_pif_pms_monitor_1: Reg<CORE_1_PIF_PMS_MONITOR_1_SPEC>

0x24c - core1 permission report register 1.

core_1_pif_pms_monitor_2: Reg<CORE_1_PIF_PMS_MONITOR_2_SPEC>

0x250 - core1 permission report register 2.

core_1_pif_pms_monitor_3: Reg<CORE_1_PIF_PMS_MONITOR_3_SPEC>

0x254 - core1 permission report register 3.

core_1_pif_pms_monitor_4: Reg<CORE_1_PIF_PMS_MONITOR_4_SPEC>

0x258 - core1 permission report register 4.

core_1_pif_pms_monitor_5: Reg<CORE_1_PIF_PMS_MONITOR_5_SPEC>

0x25c - core1 permission report register 5.

core_1_pif_pms_monitor_6: Reg<CORE_1_PIF_PMS_MONITOR_6_SPEC>

0x260 - core1 permission report register 6.

core_1_vecbase_override_lock: Reg<CORE_1_VECBASE_OVERRIDE_LOCK_SPEC>

0x264 - core1 vecbase override configuration register 0

core_1_vecbase_override_0: Reg<CORE_1_VECBASE_OVERRIDE_0_SPEC>

0x268 - core1 vecbase override configuration register 0

core_1_vecbase_override_1: Reg<CORE_1_VECBASE_OVERRIDE_1_SPEC>

0x26c - core1 vecbase override configuration register 1

core_1_vecbase_override_2: Reg<CORE_1_VECBASE_OVERRIDE_2_SPEC>

0x270 - core1 vecbase override configuration register 1

core_1_toomanyexceptions_m_override_0: Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>

0x274 - core1 toomanyexception override configuration register 0.

core_1_toomanyexceptions_m_override_1: Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>

0x278 - core1 toomanyexception override configuration register 1.

backup_bus_pms_constrain_0: Reg<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC>

0x27c - BackUp access peripherals permission configuration register 0.

backup_bus_pms_constrain_1: Reg<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC>

0x280 - BackUp access peripherals permission configuration register 1.

backup_bus_pms_constrain_2: Reg<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC>

0x284 - BackUp access peripherals permission configuration register 2.

backup_bus_pms_constrain_3: Reg<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC>

0x288 - BackUp access peripherals permission configuration register 3.

backup_bus_pms_constrain_4: Reg<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC>

0x28c - BackUp access peripherals permission configuration register 4.

backup_bus_pms_constrain_5: Reg<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC>

0x290 - BackUp access peripherals permission configuration register 5.

backup_bus_pms_constrain_6: Reg<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC>

0x294 - BackUp access peripherals permission configuration register 6.

backup_bus_pms_monitor_0: Reg<BACKUP_BUS_PMS_MONITOR_0_SPEC>

0x298 - BackUp permission report register 0.

backup_bus_pms_monitor_1: Reg<BACKUP_BUS_PMS_MONITOR_1_SPEC>

0x29c - BackUp permission report register 1.

backup_bus_pms_monitor_2: Reg<BACKUP_BUS_PMS_MONITOR_2_SPEC>

0x2a0 - BackUp permission report register 2.

backup_bus_pms_monitor_3: Reg<BACKUP_BUS_PMS_MONITOR_3_SPEC>

0x2a4 - BackUp permission report register 3.

edma_boundary_lock: Reg<EDMA_BOUNDARY_LOCK_SPEC>

0x2a8 - EDMA boundary lock register.

edma_boundary_0: Reg<EDMA_BOUNDARY_0_SPEC>

0x2ac - EDMA boundary 0 configuration

edma_boundary_1: Reg<EDMA_BOUNDARY_1_SPEC>

0x2b0 - EDMA boundary 1 configuration

edma_boundary_2: Reg<EDMA_BOUNDARY_2_SPEC>

0x2b4 - EDMA boundary 2 configuration

edma_pms_spi2_lock: Reg<EDMA_PMS_SPI2_LOCK_SPEC>

0x2b8 - EDMA-SPI2 permission lock register.

edma_pms_spi2: Reg<EDMA_PMS_SPI2_SPEC>

0x2bc - EDMA-SPI2 permission control register.

edma_pms_spi3_lock: Reg<EDMA_PMS_SPI3_LOCK_SPEC>

0x2c0 - EDMA-SPI3 permission lock register.

edma_pms_spi3: Reg<EDMA_PMS_SPI3_SPEC>

0x2c4 - EDMA-SPI3 permission control register.

edma_pms_uhci0_lock: Reg<EDMA_PMS_UHCI0_LOCK_SPEC>

0x2c8 - EDMA-UHCI0 permission lock register.

edma_pms_uhci0: Reg<EDMA_PMS_UHCI0_SPEC>

0x2cc - EDMA-UHCI0 permission control register.

edma_pms_i2s0_lock: Reg<EDMA_PMS_I2S0_LOCK_SPEC>

0x2d0 - EDMA-I2S0 permission lock register.

edma_pms_i2s0: Reg<EDMA_PMS_I2S0_SPEC>

0x2d4 - EDMA-I2S0 permission control register.

edma_pms_i2s1_lock: Reg<EDMA_PMS_I2S1_LOCK_SPEC>

0x2d8 - EDMA-I2S1 permission lock register.

edma_pms_i2s1: Reg<EDMA_PMS_I2S1_SPEC>

0x2dc - EDMA-I2S1 permission control register.

edma_pms_lcd_cam_lock: Reg<EDMA_PMS_LCD_CAM_LOCK_SPEC>

0x2e0 - EDMA-LCD/CAM permission lock register.

edma_pms_lcd_cam: Reg<EDMA_PMS_LCD_CAM_SPEC>

0x2e4 - EDMA-LCD/CAM permission control register.

edma_pms_aes_lock: Reg<EDMA_PMS_AES_LOCK_SPEC>

0x2e8 - EDMA-AES permission lock register.

edma_pms_aes: Reg<EDMA_PMS_AES_SPEC>

0x2ec - EDMA-AES permission control register.

edma_pms_sha_lock: Reg<EDMA_PMS_SHA_LOCK_SPEC>

0x2f0 - EDMA-SHA permission lock register.

edma_pms_sha: Reg<EDMA_PMS_SHA_SPEC>

0x2f4 - EDMA-SHA permission control register.

edma_pms_adc_dac_lock: Reg<EDMA_PMS_ADC_DAC_LOCK_SPEC>

0x2f8 - EDMA-ADC/DAC permission lock register.

edma_pms_adc_dac: Reg<EDMA_PMS_ADC_DAC_SPEC>

0x2fc - EDMA-ADC/DAC permission control register.

edma_pms_rmt_lock: Reg<EDMA_PMS_RMT_LOCK_SPEC>

0x300 - EDMA-RMT permission lock register.

edma_pms_rmt: Reg<EDMA_PMS_RMT_SPEC>

0x304 - EDMA-RMT permission control register.

clock_gate_reg: Reg<CLOCK_GATE_REG_SPEC>

0x308 - Sensitive module clock gate configuration register.

rtc_pms: Reg<RTC_PMS_SPEC>

0x30c - RTC coprocessor permission register.

date: Reg<DATE_SPEC>

0xffc - Sensitive version register.

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