Module esp32s3::debug_assist::core_1_interrupt_ena

Core1 monitor enable configuration register

Structs

CORE_1_AREA_DRAM0_0_RD_ENA_R

Field CORE_1_AREA_DRAM0_0_RD_ENA reader - Core1 dram0 area0 read monitor enable

CORE_1_AREA_DRAM0_0_RD_ENA_W

Field CORE_1_AREA_DRAM0_0_RD_ENA writer - Core1 dram0 area0 read monitor enable

CORE_1_AREA_DRAM0_0_WR_ENA_R

Field CORE_1_AREA_DRAM0_0_WR_ENA reader - Core1 dram0 area0 write monitor enable

CORE_1_AREA_DRAM0_0_WR_ENA_W

Field CORE_1_AREA_DRAM0_0_WR_ENA writer - Core1 dram0 area0 write monitor enable

CORE_1_AREA_DRAM0_1_RD_ENA_R

Field CORE_1_AREA_DRAM0_1_RD_ENA reader - Core1 dram0 area1 read monitor enable

CORE_1_AREA_DRAM0_1_RD_ENA_W

Field CORE_1_AREA_DRAM0_1_RD_ENA writer - Core1 dram0 area1 read monitor enable

CORE_1_AREA_DRAM0_1_WR_ENA_R

Field CORE_1_AREA_DRAM0_1_WR_ENA reader - Core1 dram0 area1 write monitor enable

CORE_1_AREA_DRAM0_1_WR_ENA_W

Field CORE_1_AREA_DRAM0_1_WR_ENA writer - Core1 dram0 area1 write monitor enable

CORE_1_AREA_PIF_0_RD_ENA_R

Field CORE_1_AREA_PIF_0_RD_ENA reader - Core1 PIF area0 read monitor enable

CORE_1_AREA_PIF_0_RD_ENA_W

Field CORE_1_AREA_PIF_0_RD_ENA writer - Core1 PIF area0 read monitor enable

CORE_1_AREA_PIF_0_WR_ENA_R

Field CORE_1_AREA_PIF_0_WR_ENA reader - Core1 PIF area0 write monitor enable

CORE_1_AREA_PIF_0_WR_ENA_W

Field CORE_1_AREA_PIF_0_WR_ENA writer - Core1 PIF area0 write monitor enable

CORE_1_AREA_PIF_1_RD_ENA_R

Field CORE_1_AREA_PIF_1_RD_ENA reader - Core1 PIF area1 read monitor enable

CORE_1_AREA_PIF_1_RD_ENA_W

Field CORE_1_AREA_PIF_1_RD_ENA writer - Core1 PIF area1 read monitor enable

CORE_1_AREA_PIF_1_WR_ENA_R

Field CORE_1_AREA_PIF_1_WR_ENA reader - Core1 PIF area1 write monitor enable

CORE_1_AREA_PIF_1_WR_ENA_W

Field CORE_1_AREA_PIF_1_WR_ENA writer - Core1 PIF area1 write monitor enable

CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R

Field CORE_1_DRAM0_EXCEPTION_MONITOR_ENA reader - DBUS busy monitor enbale

CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W

Field CORE_1_DRAM0_EXCEPTION_MONITOR_ENA writer - DBUS busy monitor enbale

CORE_1_INTERRUPT_ENA_SPEC

Core1 monitor enable configuration register

CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R

Field CORE_1_IRAM0_EXCEPTION_MONITOR_ENA reader - IBUS busy monitor enable

CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W

Field CORE_1_IRAM0_EXCEPTION_MONITOR_ENA writer - IBUS busy monitor enable

CORE_1_SP_SPILL_MAX_ENA_R

Field CORE_1_SP_SPILL_MAX_ENA reader - Core1 stackpoint underflow monitor enable

CORE_1_SP_SPILL_MAX_ENA_W

Field CORE_1_SP_SPILL_MAX_ENA writer - Core1 stackpoint underflow monitor enable

CORE_1_SP_SPILL_MIN_ENA_R

Field CORE_1_SP_SPILL_MIN_ENA reader - Core1 stackpoint overflow monitor enable

CORE_1_SP_SPILL_MIN_ENA_W

Field CORE_1_SP_SPILL_MIN_ENA writer - Core1 stackpoint overflow monitor enable

R

Register CORE_1_INTERRUPT_ENA reader

W

Register CORE_1_INTERRUPT_ENA writer