Struct esp32s3::timg0::regclk::REGCLK_SPEC

pub struct REGCLK_SPEC;

Timer group clock gate register

This register you can [read] (crate::generic::Reg::read), [write_with_zero] (crate::generic::Reg::write_with_zero), [reset] (crate::generic::Reg::reset), write (crate::generic::Reg::write), [modify] (crate::generic::Reg::modify). See [API] (https://docs.rs/svd2rust/#read–modify–write-api).

For information about available fields see [regclk] (index.html) module

Trait Implementations

impl Readable for REGCLK_SPEC

read() method returns [regclk::R] (R) reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for REGCLK_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for REGCLK_SPEC

reset() method sets REGCLK to value 0

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for REGCLK_SPEC

write(|w| ..) method takes [regclk::W] (W) writer structure

type Writer = W

Writer type argument to write, et al.