Struct esp32s3::sensitive::core_0_pif_pms_constrain_1::R

pub struct R(_);

Register CORE_0_PIF_PMS_CONSTRAIN_1 reader

Implementations

impl R

pub fn core_0_pif_pms_constrain_world_0_uart(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R

Bits 0:1 - Core0 access uart permission in world0.

pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R

Bits 2:3 - Core0 access g0spi_1 permission in world0.

pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R

Bits 4:5 - Core0 access g0spi_0 permission in world0.

pub fn core_0_pif_pms_constrain_world_0_gpio(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R

Bits 6:7 - Core0 access gpio permission in world0.

pub fn core_0_pif_pms_constrain_world_0_fe2(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R

Bits 8:9 - Core0 access fe2 permission in world0.

pub fn core_0_pif_pms_constrain_world_0_fe(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R

Bits 10:11 - Core0 access fe permission in world0.

pub fn core_0_pif_pms_constrain_world_0_rtc(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R

Bits 14:15 - Core0 access rtc permission in world0.

pub fn core_0_pif_pms_constrain_world_0_io_mux(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R

Bits 16:17 - Core0 access io_mux permission in world0.

pub fn core_0_pif_pms_constrain_world_0_hinf(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R

Bits 20:21 - Core0 access hinf permission in world0.

pub fn core_0_pif_pms_constrain_world_0_misc(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R

Bits 24:25 - Core0 access misc permission in world0.

pub fn core_0_pif_pms_constrain_world_0_i2c(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R

Bits 26:27 - Core0 access i2c permission in world0.

pub fn core_0_pif_pms_constrain_world_0_i2s0(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R

Bits 28:29 - Core0 access i2s0 permission in world0.

pub fn core_0_pif_pms_constrain_world_0_uart1(
    &self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R

Bits 30:31 - Core0 access uart1 permission in world0.

Methods from Deref<Target = R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>> for R

fn from(reader: R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>) -> Self

Converts to this type from the input type.