Struct esp32s3::extmem::icache_autoload_ctrl::W

pub struct W(_);

Register ICACHE_AUTOLOAD_CTRL writer

Implementations

impl W

pub fn icache_autoload_sct0_ena(&mut self) -> ICACHE_AUTOLOAD_SCT0_ENA_W<'_>

Bit 0 - The bits are used to enable the first section for autoload operation.

pub fn icache_autoload_sct1_ena(&mut self) -> ICACHE_AUTOLOAD_SCT1_ENA_W<'_>

Bit 1 - The bits are used to enable the second section for autoload operation.

pub fn icache_autoload_ena(&mut self) -> ICACHE_AUTOLOAD_ENA_W<'_>

Bit 2 - The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.

pub fn icache_autoload_order(&mut self) -> ICACHE_AUTOLOAD_ORDER_W<'_>

Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending.

pub fn icache_autoload_rqst(&mut self) -> ICACHE_AUTOLOAD_RQST_W<'_>

Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.

pub fn icache_autoload_size(&mut self) -> ICACHE_AUTOLOAD_SIZE_W<'_>

Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation.

pub fn icache_autoload_buffer_clear(
    &mut self
) -> ICACHE_AUTOLOAD_BUFFER_CLEAR_W<'_>

Bit 9 - The bit is used to clear autoload buffer in icache.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<ICACHE_AUTOLOAD_CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<ICACHE_AUTOLOAD_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<ICACHE_AUTOLOAD_CTRL_SPEC>> for W

fn from(writer: W<ICACHE_AUTOLOAD_CTRL_SPEC>) -> Self

Converts to this type from the input type.