pub struct W(_);Expand description
Register DIN_NUM writer
Implementations§
source§impl W
impl W
sourcepub fn din0_num(&mut self) -> DIN0_NUM_W<'_, 0>
pub fn din0_num(&mut self) -> DIN0_NUM_W<'_, 0>
Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din1_num(&mut self) -> DIN1_NUM_W<'_, 2>
pub fn din1_num(&mut self) -> DIN1_NUM_W<'_, 2>
Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din2_num(&mut self) -> DIN2_NUM_W<'_, 4>
pub fn din2_num(&mut self) -> DIN2_NUM_W<'_, 4>
Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din3_num(&mut self) -> DIN3_NUM_W<'_, 6>
pub fn din3_num(&mut self) -> DIN3_NUM_W<'_, 6>
Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din4_num(&mut self) -> DIN4_NUM_W<'_, 8>
pub fn din4_num(&mut self) -> DIN4_NUM_W<'_, 8>
Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din5_num(&mut self) -> DIN5_NUM_W<'_, 10>
pub fn din5_num(&mut self) -> DIN5_NUM_W<'_, 10>
Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din6_num(&mut self) -> DIN6_NUM_W<'_, 12>
pub fn din6_num(&mut self) -> DIN6_NUM_W<'_, 12>
Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.
sourcepub fn din7_num(&mut self) -> DIN7_NUM_W<'_, 14>
pub fn din7_num(&mut self) -> DIN7_NUM_W<'_, 14>
Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state.