Struct esp32s3::spi2::ctrl::W

pub struct W(_);

Register CTRL writer

Implementations

impl W

pub fn dummy_out(&mut self) -> DUMMY_OUT_W<'_, 3>

Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.

pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, 5>

Bit 5 - Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, 6>

Bit 6 - Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

pub fn faddr_oct(&mut self) -> FADDR_OCT_W<'_, 7>

Bit 7 - Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fcmd_dual(&mut self) -> FCMD_DUAL_W<'_, 8>

Bit 8 - Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<'_, 9>

Bit 9 - Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<'_, 10>

Bit 10 - Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.

pub fn fread_dual(&mut self) -> FREAD_DUAL_W<'_, 14>

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.

pub fn fread_quad(&mut self) -> FREAD_QUAD_W<'_, 15>

Bit 15 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.

pub fn fread_oct(&mut self) -> FREAD_OCT_W<'_, 16>

Bit 16 - In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.

pub fn q_pol(&mut self) -> Q_POL_W<'_, 18>

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.

pub fn d_pol(&mut self) -> D_POL_W<'_, 19>

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.

pub fn hold_pol(&mut self) -> HOLD_POL_W<'_, 20>

Bit 20 - SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

pub fn wp_pol(&mut self) -> WP_POL_W<'_, 21>

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.

pub fn rd_bit_order(&mut self) -> RD_BIT_ORDER_W<'_, 23>

Bits 23:24 - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.

pub fn wr_bit_order(&mut self) -> WR_BIT_ORDER_W<'_, 25>

Bits 25:26 - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CTRL_SPEC>> for W

fn from(writer: W<CTRL_SPEC>) -> Self

Converts to this type from the input type.